In digital electronics, adder and subtractor are the two most basic arithmetic combinational circuits. The adder is a combinational arithmetic circuit used to perform addition of two or more binary numbers. Whereas, the subtractor is a combination arithmetic circuit used to perform subtraction of two binary numbers.

Depending on the form in which the addition and subtraction of binary numbers are executed, the adder and subtractor are classified into following types −

• Serial Adder
• Parallel Adder
• Serial Subtractor
• Parallel Subtractor

This tutorial is meant for explaining Parallel Adder and Parallel Subtractor. But before that let us first discuss the rules of Boolean algebra followed to perform the binary addition and subtraction.

Binary Addition

The following rules are followed while performing binary addition −

Binary Subtraction

The following rules are to be followed while performing binary subtraction −

Now, let us discuss the parallel adder and parallel subtractor in detail.

What is Parallel Adder?

A digital circuit that adds two binary numbers of any bit length in parallel form and produces the sum of those number in parallel form is called a parallel adder.

A parallel adder basically consists of full adders in a chain form as shown in Figure 1. Here, the output bit of each full adder is connected to the input carry terminal of the next full adder circuit in the chain.

The parallel adder shown in Figure 1 is a 4-bit parallel adder as it can add two binary number of 4 bits. Although, we can design a parallel adder circuit for any number of bits by increasing the number of full adders in the chain.

In the above parallel adder circuit, the bit A is representing the augend bits and B is representing the addend bits. The first input carry bit to the parallel adder is C_in and the output carry bit of the parallel adder is C₄. The output sum bits are designated by S. We can also construct a parallel adder in the form of an IC. For example, when the 4-bit parallel adder is formed in the IC form, then it will have four terminals for augend bits, 4 terminals for addend bits, 4 terminals for sum bits, and 2 terminals for input and output carry bits.

Working of Parallel Adder

The parallel adder shown in figure-1 performs the binary addition of two numbers as per the following step −

Step 1 − Firstly, the full adder circuit FA₁ adds the bits A₁ and B₁ along with the input carry bit Cin to produce the sum bit S₁, where it is the LSB (Least Significant Bit) of the output sum. At this stage, a carry bit C₁ is generated which is transferred to the next full adder circuit in the chain.

Step 2 − The full adder circuit FA₂ adds bits A₂ and B₂ along with the carry bit C₁ from the previous addition. It produces the sum bit S₂ which is the second bit of the output sum, and a carry bit C₂ is also produced which again forwarded to the next full adder FA₃.

Step 3 − The full adder circuit FA₃ adds inputs bits A₃ and B₃ along with the carry bit C₂ from previous addition to produce sum bit S₃ and carry bit C₃.

Step 4 − The full adder FA₄ adds input bits A₄ and B₄ along with the carry bit C₃ forward from FA₃. It generates the last sum bit S₄ and a last carry bit C₄.

Step 5 − The output sum of the parallel adder is then given by,

$$\mathrm{S_{out} \: = \: C_{4} \: S_{4} \: S_{3} \: S_{2} \: S_{1}}$$

What is Parallel Subtractor?

A digital arithmetic circuit which is used to find the arithmetic difference of two binary numbers in parallel form is called a parallel subtractor.

We can implement a parallel subtractor in several ways such as combining half subtractors and full subtractors, all full subtractors, all full adders, etc. Here, we have realized a 4-bit parallel subtractor using all full adders with subtrahend bit complemented as shown in Figure 2.

This is the 4-bit parallel subtractor, however, we can implement a parallel subtractor by adding any number of full adders in the chain of the circuit shown in figure-2.

The binary subtraction of two binary numbers can be conveniently accomplished by means of 1”s or 2”s complement. Where, the complement method converts the subtraction operation in simple addition operation.

The 2”s complement of binary numbers is obtained by taking the 1”s complement and adding 1 to the least significant pair of bits. The 1”s complement can be implemented with the help of a NOT gate (inverter).

Working of Parallel Subtractor

The parallel subtractor shown in above figure-2 carries out the subtraction of two binary numbers as per the following steps −

Step 1 − Firstly, the 1”s complement of bit B₁ obtained using an inverter and a 1 (C_in) are added to obtain the 2”s complement of the bit B₁. Then, this 2”s complemented B₁ is further added to A₁. This will produce first bit of the output difference designated by S₁, and a carry bit C₁ which is connected to the input carry of the FA₂.

Step 2 − The full adder FA₂ uses the input carry bit C₁ to add with its input bit A₂ and the 2”s complement of the input bit B₂ to produce the second difference bit (S₂) and the carry bit C₂.

Step 3 − The full adder FA₃ uses the input carry bit C₂ to add with its input bit A₃ and the 2”s complement of the input bit B₃ to produce the third difference bit (S₃) and the carry bit C₃.

Step 4 − Finally, the full adder FA₄ uses the carry bit C₃ to add with its input bit A₄ and the 2”s complement of the input bit B₄ to produce the last difference bit (S₄) and last carry bit C₄.

Once all the result bits are produced, they are expressed to give the difference of the two binary numbers as S₄S₃S₂S₁ and borrow bit C₄.

Conclusion

This is all about parallel adder and parallel subtractor in digital electronics. The most significant advantage of the parallel adder and subtractor is that they perform the arithmetic addition and subtraction of two binary numbers faster as compared to the serial adder and subtractor.