Category: vlsi Design

Combinational MOS Logic Circuits Combinational logic circuits or gates, which perform Boolean operations on multiple input variables and determine the outputs as Boolean functions of the inputs, are the basic building blocks of all digital systems. We will examine simple circuit configurations such as two-input NAND and NOR gates and then expand our analysis to more general cases of multiple-input circuit structures. Next, the CMOS logic circuits will be presented in a similar fashion. We will stress the similarities and differences between the nMOS depletion-load logic and CMOS logic circuits and point out the advantages of CMOS gates with examples. In its most general form, a combinational logic circuit, or gate, performing a Boolean function can be represented as a multiple-input, single-output system, as depicted in the figure. Node voltages, referenced to the ground potential, represent all input variables. Using positive logic convention, the Boolean (or logic) value of “1” can be represented by a high voltage of VDD, and the Boolean (or logic) value of “0” can be represented by a low voltage of 0. The output node is loaded with a capacitance CL, which represents the combined capacitances of the parasitic device in the circuit. CMOS Logic Circuits CMOS Two input NOR Gate The circuit consists of a parallel-connected n-net and a series-connected complementary p-net. The input voltages VX and VY are applied to the gates of one nMOS and one pMOS transistor. When either one or both inputs are high, i.e., when the n-net creates a conducting path between the output node and the ground, the p-net is cut—off. If both input voltages are low, i.e., the n-net is cut-off, then the p-net creates a conducting path between the output node and the supply voltage. For any given input combination, the complementary circuit structure is such that the output is connected either to VDD or to ground via a low-resistance path and a DC current path between the VDD and ground is not established for any input combinations. The output voltage of the CMOS, two input NOR gate will get a logic-low voltage of VOL = 0 and a logic-high voltage of VOH = VDD. The equation of the switching threshold voltage Vth is given by $$V_{th}left ( NOR2 right ) = frac{V_{T,n}+frac{1}{2}sqrt{frac{k_{p}}{k_{n}}left ( V_{DD}-left | V_{T,p} right | right )}}{1+frac{1}{2}sqrt{frac{k_{p}}{k_{n}}}}$$ Layout of CMOS 2-input NOR Gate The figure shows a sample layout of CMOS 2-input NOR gate, using single-layer metal and single-layer polysilicon. The features of this layout are − Single vertical polylines for each input Single active shapes for N and P devices, respectively Metal buses running horizontal The stick diagram for the CMOS N0R2 gate is shown in the figure given below; which corresponds directly to the layout, but does not contain W and L information. The diffusion areas are depicted by rectangles, the metal connections and solid lines and circles, respectively represent contacts, and the crosshatched strips represent the polysilicon columns. Stick diagram is useful for planning optimum layout topology. CMOS Two-input NAND Gate The circuit diagram of the two input CMOS NAND gate is given in the figure below. The principle of operation of the circuit is exact dual of the CMOS two input NOR operation. The n – net consisting of two series connected nMOS transistor creates a conducting path between the output node and the ground, if both input voltages are logic high. Both of the parallelly connected pMOS transistor in p-net will be off. For all other input combination, either one or both of the pMOS transistor will be turn ON, while p – net is cut off, thus, creating a current path between the output node and the power supply voltage. The switching threshold for this gate is obtained as − $$V_{th}left ( NAND2 right ) = frac{V_{T,n}+2sqrt{frac{k_{p}}{k_{n}}left ( V_{DD}-left | V_{T,p} right | right )}}{1+2sqrt{frac{k_{p}}{k_{n}}}}$$ The features of this layout are as follows − Single polysilicon lines for inputs run vertically across both N and P active regions. Single active shapes are used for building both nMOS devices and both pMOS devices. Power bussing is running horizontal across top and bottom of layout. Output wires runs horizontal for easy connection to neighboring circuit. Complex Logic Circuits NMOS Depletion Load Complex Logic Gate To realize complex functions of multiple input variables, the basic circuit structures and design principles developed for NOR and NAND can be extended to complex logic gates. The ability to realize complex logic functions, using a small number of transistors is one of the most attractive features of nMOS and CMOS logic circuits. Consider the following Boolean function as an example. $$overline{Z=Pleft ( S+T right )+QR}$$ The nMOS depletion-load complex logic gate used to realize this function is shown in figure. In this figure, the left nMOS driver branch of three driver transistors is used to perform the logic function P (S + T), while the right-hand side branch performs the function QR. By connecting the two branches in parallel, and by placing the load transistor between the output node and the supply voltage VDD, we obtain the given complex function. Each input variable is assigned to only one driver. Inspection of the circuit topology gives simple design principles of the pull-down network − OR operations are performed by parallel-connected drivers. AND operations are performed by series-connected drivers. Inversion is provided by the nature of MOS circuit operation. If all input variables are logic-high in the circuit realizing the function, the equivalent driver (W/L) ratio of the pull-down network consisting of five nMOS transistors is $$frac{W}{L}=frac{1}{frac{1}{left ( W/L right )Q}+frac{1}{left ( W/L right )R}}+frac{1}{frac{1}{left ( W/L right )P}+frac{1}{left ( W/L right )S+left ( W/L right )Q}}$$ Complex CMOS Logic Gates The realization of the n-net, or pull-down network, is based on the same basic design principles examined for nMOS depletion-load complex logic gate. The pMOS pull-up network must be the dual network of the n-net. It means all parallel connections in the nMOS network will correspond to a series connection in the pMOS network,

VLSI Design Tutorial Job Search Over the past several years, Silicon CMOS technology has become the dominant fabrication process for relatively high performance and cost effective VLSI circuits. The revolutionary nature of these developments is understood by the rapid growth in which the number of transistors integrated on circuit on single chip. In this tutorial we are providing concept of MOS integrated circuits and coding of VHDL and Verilog language. Audience This reference has been prepared for the students who want to know about the VLSI Technology. The students will be able to know about the VHDL and Verilog program coding. Prerequisites Before you start proceeding with this tutorial, we make an assumption that you are already aware of the basic concepts of Digital Electronics. Learning working make money

VLSI Design – MOS Transistor Complementary MOSFET (CMOS) technology is widely used today to form circuits in numerous and varied applications. Today’s computers, CPUs and cell phones make use of CMOS due to several key advantages. CMOS offers low power dissipation, relatively high speed, high noise margins in both states, and will operate over a wide range of source and input voltages (provided the source voltage is fixed) For the processes we will discuss, the type of transistor available is the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). These transistors are formed as a ‘sandwich’ consisting of a semiconductor layer, usually a slice, or wafer, from a single crystal of silicon; a layer of silicon dioxide (the oxide) and a layer of metal. Structure of a MOSFET As shown in the figure, MOS structure contains three layers − The Metal Gate Electrode The Insulating Oxide Layer (SiO2) P – type Semiconductor (Substrate) MOS structure forms a capacitor, with gate and substrate are as two plates and oxide layer as the dielectric material. The thickness of dielectric material (SiO2) is usually between 10 nm and 50 nm. Carrier concentration and distribution within the substrate can be manipulated by external voltage applied to gate and substrate terminal. Now, to understand the structure of MOS, first consider the basic electric properties of P – Type semiconductor substrate. Concentration of carrier in semiconductor material is always following the Mass Action Law. Mass Action Law is given by − $$n.p=n_{i}^{2}$$ Where, n is carrier concentration of electrons p is carrier concentration of holes ni is intrinsic carrier concentration of Silicon Now assume that substrate is equally doped with acceptor (Boron) concentration NA. So, electron and hole concentration in p–type substrate is $$n_{po}=frac{n_{i}^{2}}{N_{A}}$$ $$p_{po}=N_{A}$$ Here, doping concentration NA is (1015 to 1016 cm−3) greater than intrinsic concentration ni. Now, to understand the MOS structure, consider the energy level diagram of p–type silicon substrate. As shown in the figure, the band gap between conduction band and valance band is 1.1eV. Here, Fermi potential ΦF is the difference between intrinsic Fermi level (Ei) and Fermi level (EFP). Where Fermi level EF depends on the doping concentration. Fermi potential ΦF is the difference between intrinsic Fermi level (Ei) and Fermi level (EFP). Mathematically, $$Phi_{Fp}=frac{E_{F}-E_{i}}{q}$$ The potential difference between conduction band and free space is called electron affinity and is denoted by qx. So, energy required for an electron to move from Fermi level to free space is called work function (qΦS) and it is given by $$qPhi _{s}=(E_{c}-E_{F})+qx$$ The following figure shows the energy band diagram of components that make up the MOS. As shown in the above figure, insulating SiO2 layer has large energy band gap of 8eV and work function is 0.95 eV. Metal gate has work function of 4.1eV. Here, the work functions are different so it will create voltage drop across the MOS system. The figure given below shows the combined energy band diagram of MOS system. As shown in this figure, the fermi potential level of metal gate and semiconductor (Si) are at same potential. Fermi potential at surface is called surface potential ΦS and it is smaller than Fermi potential ΦF in magnitude. Working of a MOSFET MOSFET consists of a MOS capacitor with two p-n junctions placed closed to the channel region and this region is controlled by gate voltage. To make both the p-n junction reverse biased, substrate potential is kept lower than the other three terminals potential. If the gate voltage will be increased beyond the threshold voltage (VGS>VTO), inversion layer will be established on the surface and n – type channel will be formed between the source and drain. This n – type channel will carry the drain current according to the VDS value. For different value of VDS, MOSFET can be operated in different regions as explained below. Linear Region At VDS = 0, thermal equilibrium exists in the inverted channel region and drain current ID = 0. Now if small drain voltage, VDS > 0 is applied, a drain current proportional to the VDS will start to flow from source to drain through the channel. The channel gives a continuous path for the flow of current from source to drain. This mode of operation is called linear region. The cross sectional view of an n-channel MOSFET, operating in linear region, is shown in the figure given below. At the Edge of Saturation Region Now if the VDS is increased, charges in the channel and channel depth decrease at the end of drain. For VDS = VDSAT, the charges in the channel is reduces to zero, which is called pinch – off point. The cross sectional view of n-channel MOSFET operating at the edge of saturation region is shown in the figure given below. Saturation Region For VDS>VDSAT, a depleted surface forms near to drain, and by increasing the drain voltage this depleted region extends to source. This mode of operation is called Saturation region. The electrons coming from the source to the channel end, enter in the drain – depletion region and are accelerated towards the drain in high electric field. MOSFET Current – Voltage Characteristics To understand the current – voltage characteristic of MOSFET, approximation for the channel is done. Without this approximation, the three dimension analysis of MOS system becomes complex. The Gradual Channel Approximation (GCA) for current – voltage characteristic will reduce the analysis problem. Gradual Channel Approximation (GCA) Consider the cross sectional view of n channel MOSFET operating in the linear mode. Here, source and substrate are connected to the ground. VS = VB = 0. The gate – to – source (VGS) and drain – to – source voltage (VDS) voltage are the external parameters that control the drain current ID. The voltage, VGS is set to a voltage greater than the threshold voltage VTO, to create a channel between the source and drain. As shown in the figure, x – direction is perpendicular to the surface and y – direction is parallel

VLSI Design – VHDL Introduction VHDL stands for very high-speed integrated circuit hardware description language. It is a programming language used to model a digital system by dataflow, behavioral and structural style of modeling. This language was first introduced in 1981 for the department of Defense (DoD) under the VHSIC program. Describing a Design In VHDL an entity is used to describe a hardware module. An entity can be described using, Entity declaration Architecture Configuration Package declaration Package body Let’s see what are these? Entity Declaration It defines the names, input output signals and modes of a hardware module. Syntax − entity entity_name is Port declaration; end entity_name; An entity declaration should start with ‘entity’ and end with ‘end’ keywords. The direction will be input, output or inout. In Port can be read Out Port can be written Inout Port can be read and written Buffer Port can be read and written, it can have only one source. Architecture − Architecture can be described using structural, dataflow, behavioral or mixed style. Syntax − architecture architecture_name of entity_name architecture_declarative_part; begin Statements; end architecture_name; Here, we should specify the entity name for which we are writing the architecture body. The architecture statements should be inside the ‘begin’ and ‘énd’ keyword. Architecture declarative part may contain variables, constants, or component declaration. Data Flow Modeling In this modeling style, the flow of data through the entity is expressed using concurrent (parallel) signal. The concurrent statements in VHDL are WHEN and GENERATE. Besides them, assignments using only operators (AND, NOT, &plus;, *, sll, etc.) can also be used to construct code. Finally, a special kind of assignment, called BLOCK, can also be employed in this kind of code. In concurrent code, the following can be used − Operators The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN); The GENERATE statement; The BLOCK statement Behavioral Modeling In this modeling style, the behavior of an entity as set of statements is executed sequentially in the specified order. Only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are sequential. PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code that are executed sequentially. However, as a whole, any of these blocks is still concurrent with any other statements placed outside it. One important aspect of behavior code is that it is not limited to sequential logic. Indeed, with it, we can build sequential circuits as well as combinational circuits. The behavior statements are IF, WAIT, CASE, and LOOP. VARIABLES are also restricted and they are supposed to be used in sequential code only. VARIABLE can never be global, so its value cannot be passed out directly. Structural Modeling In this modeling, an entity is described as a set of interconnected components. A component instantiation statement is a concurrent statement. Therefore, the order of these statements is not important. The structural style of modeling describes only an interconnection of components (viewed as black boxes), without implying any behavior of the components themselves nor of the entity that they collectively represent. In Structural modeling, architecture body is composed of two parts − the declarative part (before the keyword begin) and the statement part (after the keyword begin). Logic Operation – AND GATE X Y Z 0 0 0 0 1 0 1 0 0 1 1 1 VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity and1 is port(x,y:in bit ; z:out bit); end and1; architecture virat of and1 is begin z<=x and y; end virat; Waveforms Logic Operation – OR Gate X Y Z 0 0 0 0 1 1 1 0 1 1 1 1 VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity or1 is port(x,y:in bit ; z:out bit); end or1; architecture virat of or1 is begin z<=x or y; end virat; Waveforms Logic Operation – NOT Gate X Y 0 1 1 0 VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity not1 is port(x:in bit ; y:out bit); end not1; architecture virat of not1 is begin y<=not x; end virat; Waveforms Logic Operation – NAND Gate X Y z 0 0 1 0 1 1 1 0 1 1 1 0 VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity nand1 is port(a,b:in bit ; c:out bit); end nand1; architecture virat of nand1 is begin c<=a nand b; end virat; Waveforms Logic Operation – NOR Gate X Y z 0 0 1 0 1 0 1 0 0 1 1 0 VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity nor1 is port(a,b:in bit ; c:out bit); end nor1; architecture virat of nor1 is begin c<=a nor b; end virat; Waveforms Logic Operation – XOR Gate X Y Z 0 0 1 0 1 1 1 0 1 1 1 0 VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity xor1 is port(a,b:in bit ; c:out bit); end xor1; architecture virat of xor1 is begin c<=a xor b; end virat; Waveforms Logic Operation – X-NOR Gate X Y Z 0 0 1 0 1 1 1 0 1 1 1 0 VHDL Code: Library ieee; use ieee.std_logic_1164.all; entity xnor1 is port(a,b:in bit ; c:out bit); end xnor1; architecture virat of xnor1 is begin c<=not(a xor b); end virat; Waveforms Learning working make money

VLSI Design – Sequential MOS Logic Circuits Logic circuits are divided into two categories − (a) Combinational Circuits, and (b) Sequential Circuits. In Combinational circuits, the output depends only on the condition of the latest inputs. In Sequential circuits, the output depends not only on the latest inputs, but also on the condition of earlier inputs. Sequential circuits contain memory elements. Sequential circuits are of three types − Bistable − Bistable circuits have two stable operating points and will be in either of the states. Example − Memory cells, latches, flip-flops and registers. Monostable − Monostable circuits have only one stable operating point and even if they are temporarily perturbed to the opposite state, they will return in time to their stable operating point. Example: Timers, pulse generators. Astable − circuits have no stable operating point and oscillate between several states. Example − Ring oscillator. CMOS Logic Circuits SR Latch based on NOR Gate If the set input (S) is equal to logic “1” and the reset input is equal to logic “0.” then the output Q will be forced to logic “1”. While $overline{Q}$ is forced to logic “0”. This means the SR latch will be set, irrespective of its previous state. Similarly, if S is equal to “0” and R is equal to “1” then the output Q will be forced to “0” while $overline{Q}$ is forced to “1”. This means the latch is reset, regardless of its previously held state. Finally, if both of the inputs S and R are equal to logic “1” then both output will be forced to logic “0” which conflicts with the complementarity of Q and $overline{Q}$. Therefore, this input combination is not allowed during normal operation. Truth table of NOR based SR Latch is given in table. S R Q $overline{Q}$ Operation 0 0 Q $overline{Q}$ Hold 1 0 1 0 Set 0 1 0 1 Reset 1 1 0 0 Not allowed CMOS SR latch based on NOR gate is shown in the figure given below. If the S is equal to VOH and the R is equal to VOL, both of the parallel-connected transistors M1 and M2 will be ON. The voltage on node $overline{Q}$ will assume a logic-low level of VOL = 0. At the same time, both M3 and M4 are turned off, which results in a logic-high voltage VOH at node Q. If the R is equal to VOH and the S is equal to VOL, M1 and M2 turned off and M3 and M4 turned on. SR Latch based on NAND Gate Block diagram and gate level schematic of NAND based SR latch is shown in the figure. The small circles at the S and R input terminals represents that the circuit responds to active low input signals. The truth table of NAND based SR latch is given in table S R Q Q′ 0 0 NC NC No change. Latch remained in present state. 1 0 1 0 Latch SET. 0 1 0 1 Latch RESET. 1 1 0 0 Invalid condition. If S goes to 0 (while R = 1), Q goes high, pulling $overline{Q}$ low and the latch enters Set state S = 0 then Q = 1 (if R = 1) If R goes to 0 (while S = 1), Q goes high, pulling $overline{Q}$ low and the latch is Reset R = 0 then Q = 1 (if S = 1) Hold state requires both S and R to be high. If S = R = 0 then output is not allowed, as it would result in an indeterminate state. CMOS SR Latch based on NAND Gate is shown in figure. Depletion-load nMOS SR Latch based on NAND Gate is shown in figure. The operation is similar to that of CMOS NAND SR latch. The CMOS circuit implementation has low static power dissipation and high noise margin. CMOS Logic Circuits Clocked SR Latch The figure shows a NOR-based SR latch with a clock added. The latch is responsive to inputs S and R only when CLK is high. When CLK is low, the latch retains its current state. Observe that Q changes state − When S goes high during positive CLK. On leading CLK edge after changes in S & R during CLK low time. A positive glitch in S while CLK is high When R goes high during positive CLK. CMOS AOI implementation of clocked NOR based SR latch is shown in the figure. Note that only 12 transistors required. When CLK is low, two series terminals in N tree N are open and two parallel transistors in tree P are ON, thus retaining state in the memory cell. When clock is high, the circuit becomes simply a NOR based CMOS latch which will respond to input S and R. Clocked SR Latch based on NAND Gate Circuit is implemented with four NAND gates. If this circuit is implemented with CMOS then it requires 16 transistors. The latch is responsive to S or R only if CLK is high. If both input signals and the CLK signals are active high: i.e., the latch output Q will be set when CLK = “1” S = “1” and R = “0” Similarly, the latch will be reset when CLK = “1,” S = “0,” and When CLK is low, the latch retains its present state. Clocked JK Latch The figure above shows a clocked JK latch, based on NAND gates. The disadvantage of an SR latch is that when both S and R are high, its output state becomes indeterminant. The JK latch eliminates this problem by using feedback from output to input, such that all input states of the truth table are allowable. If J = K = 0, the latch will hold its present state. If J = 1 and K = 0, the latch will set on the next positive-going clock edge, i.e. Q = 1, $overline{Q}$ = 0 If J = 0 and K = 1,