Category: microprocessor

Microprocessor – I/O Interfacing Overview ”; Previous Next In this chapter, we will discuss Memory Interfacing and IO Interfacing with 8085. Interface is the path for communication between two components. Interfacing is of two types, memory interfacing and I/O interfacing. Memory Interfacing When we are executing any instruction, we need the microprocessor to access the memory for reading instruction codes and the data stored in the memory. For this, both the memory and the microprocessor requires some signals to read from and write to registers. The interfacing process includes some key factors to match with the memory requirements and microprocessor signals. The interfacing circuit therefore should be designed in such a way that it matches the memory signal requirements with the signals of the microprocessor. IO Interfacing There are various communication devices like the keyboard, mouse, printer, etc. So, we need to interface the keyboard and other devices with the microprocessor by using latches and buffers. This type of interfacing is known as I/O interfacing. Block Diagram of Memory and I/O Interfacing 8085 Interfacing Pins Following is the list of 8085 pins used for interfacing with other devices − A15 – A8 (Higher Address Bus) AD7 – AD0(Lower Address/Data Bus) ALE RD WR READY Ways of Communication − Microprocessor with the Outside World? There are two ways of communication in which the microprocessor can connect with the outside world. Serial Communication Interface Parallel Communication interface Serial Communication Interface − In this type of communication, the interface gets a single byte of data from the microprocessor and sends it bit by bit to the other system serially and vice-a-versa. Parallel Communication Interface − In this type of communication, the interface gets a byte of data from the microprocessor and sends it bit by bit to the other systems in simultaneous (or) parallel fashion and vice-a-versa. Print Page Previous Next Advertisements ”;

Intel 8253/54 – Operational Modes ”; Previous Next 8253/54 can be operated in 6 different modes. In this chapter, we will discuss these operational modes. Mode 0 ─ Interrupt on Terminal Count It is used to generate an interrupt to the microprocessor after a certain interval. Initially the output is low after the mode is set. The output remains LOW after the count value is loaded into the counter. The process of decrementing the counter continues till the terminal count is reached, i.e., the count become zero and the output goes HIGH and will remain high until it reloads a new count. The GATE signal is high for normal counting. When GATE goes low, counting is terminated and the current count is latched till the GATE goes high again. Mode 1 – Programmable One Shot It can be used as a mono stable multi-vibrator. The gate input is used as a trigger input in this mode. The output remains high until the count is loaded and a trigger is applied. Mode 2 – Rate Generator The output is normally high after initialization. Whenever the count becomes zero, another low pulse is generated at the output and the counter will be reloaded. Mode 3 – Square Wave Generator This mode is similar to Mode 2 except the output remains low for half of the timer period and high for the other half of the period. Mode 4 − Software Triggered Mode In this mode, the output will remain high until the timer has counted to zero, at which point the output will pulse low and then go high again. The count is latched when the GATE signal goes LOW. On the terminal count, the output goes low for one clock cycle then goes HIGH. This low pulse can be used as a strobe. Mode 5 – Hardware Triggered Mode This mode generates a strobe in response to an externally generated signal. This mode is similar to mode 4 except that the counting is initiated by a signal at the gate input, which means it is hardware triggered instead of software triggered. After it is initialized, the output goes high. When the terminal count is reached, the output goes low for one clock cycle. Print Page Previous Next Advertisements ”;

Microcontrollers – Overview ”; Previous Next A microcontroller is a small and low-cost microcomputer, which is designed to perform the specific tasks of embedded systems like displaying microwave’s information, receiving remote signals, etc. The general microcontroller consists of the processor, the memory (RAM, ROM, EPROM), Serial ports, peripherals (timers, counters), etc. Difference between Microprocessor and Microcontroller The following table highlights the differences between a microprocessor and a microcontroller − Microcontroller Microprocessor Microcontrollers are used to execute a single task within an application. Microprocessors are used for big applications. Its designing and hardware cost is low. Its designing and hardware cost is high. Easy to replace. Not so easy to replace. It is built with CMOS technology, which requires less power to operate. Its power consumption is high because it has to control the entire system. It consists of CPU, RAM, ROM, I/O ports. It doesn’t consist of RAM, ROM, I/O ports. It uses its pins to interface to peripheral devices. Types of Microcontrollers Microcontrollers are divided into various categories based on memory, architecture, bits and instruction sets. Following is the list of their types − Bit Based on bit configuration, the microcontroller is further divided into three categories. 8-bit microcontroller − This type of microcontroller is used to execute arithmetic and logical operations like addition, subtraction, multiplication division, etc. For example, Intel 8031 and 8051 are 8 bits microcontroller. 16-bit microcontroller − This type of microcontroller is used to perform arithmetic and logical operations where higher accuracy and performance is required. For example, Intel 8096 is a 16-bit microcontroller. 32-bit microcontroller − This type of microcontroller is generally used in automatically controlled appliances like automatic operational machines, medical appliances, etc. Memory Based on the memory configuration, the microcontroller is further divided into two categories. External memory microcontroller − This type of microcontroller is designed in such a way that they do not have a program memory on the chip. Hence, it is named as external memory microcontroller. For example: Intel 8031 microcontroller. Embedded memory microcontroller − This type of microcontroller is designed in such a way that the microcontroller has all programs and data memory, counters and timers, interrupts, I/O ports are embedded on the chip. For example: Intel 8051 microcontroller. Instruction Set Based on the instruction set configuration, the microcontroller is further divided into two categories. CISC − CISC stands for complex instruction set computer. It allows the user to insert a single instruction as an alternative to many simple instructions. RISC − RISC stands for Reduced Instruction Set Computers. It reduces the operational time by shortening the clock cycle per instruction. Applications of Microcontrollers Microcontrollers are widely used in various different devices such as − Light sensing and controlling devices like LED. Temperature sensing and controlling devices like microwave oven, chimneys. Fire detection and safety devices like Fire alarm. Measuring devices like Volt Meter. Print Page Previous Next Advertisements ”;

8087 Numeric Data Processor ”; Previous Next 8087 numeric data processor is also known as Math co-processor, Numeric processor extension and Floating point unit. It was the first math coprocessor designed by Intel to pair with 8086/8088 resulting in easier and faster calculation. Once the instructions are identified by the 8086/8088 processor, then it is allotted to the 8087 co-processor for further execution. The data types supported by 8087 are − Binary Integers Packed decimal numbers Real numbers Temporary real format The most prominent features of 8087 numeric data processor are as follows − It supports data of type integer, float, and real types ranging from 2-10 bytes. The processing speed is so high that it can calculate multiplication of two 64-bits real numbers in ~27 µs and can also calculate square-root in ~35 µs. It follows IEEE floating point standards. 8087 Architecture 8087 Architecture is divided into two groups, i.e., Control Unit (CU) and Numeric Extension Unit (NEU). The control unit handles all the communication between the processor and the memory such as it receives and decodes instructions, reads and writes memory operands, maintains parallel queue, etc. All the coprocessor instructions are ESC instructions, i.e., they start with ‘F’, the coprocessor only executes the ESC instructions while other instructions are executed by the microprocessor. The numeric extension unit handles all the numeric processor instructions like arithmetic, logical, transcendental, and data transfer instructions. It has 8 register stack, which holds the operands for instructions and their results. The architecture of 8087 coprocessor is as follows − 8087 Pin Description Let us first take a look at the pin diagram of 8087 − The following list provides the Pin Description of 8087 − AD0 – AD15 − These are the time multiplexed address/data lines, which carry addresses during the first clock cycle and data from the second clock cycle onwards. A19 / S6 – A16/S − These lines are the time multiplexed address/status lines. It functions in a similar way to the corresponding pins of 8086. The S6, S4 and S3 are permanently high, while the S5 is permanently low. $overline{BHE}$/S7 − During the first clock cycle, the $overline{BHE}$/S7 is used to enable data on to the higher byte of the 8086 data bus and after that works as status line S7. QS1, QS0 − These are queue status input signals which provides the status of instruction queue, their conditions as shown in the following table − QS0 QS1 Status 0 0 No operation 0 1 First byte of opcode from the queue 1 0 Empty the queue 1 1 Subsequent byte from the queue INT − It is an interrupt signal, which changes to high when an unmasked exception has been received during the execution. BUSY − It is an output signal, when it is high it indicates a busy state to the CPU. READY − It is an input signal used to inform the coprocessor whether the bus is ready to receive data or not. RESET − It is an input signal used to reject the internal activities of the coprocessor and prepare it for further execution whenever required by the CPU. CLK − The CLK input provides the basic timings for the processor operation. VCC − It is a power supply signal, which requires +5V supply for the operation of the circuit. S0, S1, S2 − These are the status signals that provide the status of the operation which is used by the Bus Controller 8087 to generate memory and I/O control signals. These signals are active during the fourth clock cycle. S2 S1 S0 Queue Status 0 X X Unused 1 0 0 Unused 1 0 1 Memory read 1 1 0 Memory write 1 1 1 Passive RQ/GT1 & RQ/GT0 − These are the Request/Grant signals used by the 8087 processors to gain control of the bus from the host processor 8086/8088 for operand transfers. Print Page Previous Next Advertisements ”;

Microcontrollers – 8051 Pin Description ”; Previous Next The pin diagram of 8051 microcontroller looks as follows − Pins 1 to 8 − These pins are known as Port 1. This port doesn’t serve any other functions. It is internally pulled up, bi-directional I/O port. Pin 9 − It is a RESET pin, which is used to reset the microcontroller to its initial values. Pins 10 to 17 − These pins are known as Port 3. This port serves some functions like interrupts, timer input, control signals, serial communication signals RxD and TxD, etc. Pins 18 & 19 − These pins are used for interfacing an external crystal to get the system clock. Pin 20 − This pin provides the power supply to the circuit. Pins 21 to 28 − These pins are known as Port 2. It serves as I/O port. Higher order address bus signals are also multiplexed using this port. Pin 29 − This is PSEN pin which stands for Program Store Enable. It is used to read a signal from the external program memory. Pin 30 − This is EA pin which stands for External Access input. It is used to enable/disable the external memory interfacing. Pin 31 − This is ALE pin which stands for Address Latch Enable. It is used to demultiplex the address-data signal of port. Pins 32 to 39 − These pins are known as Port 0. It serves as I/O port. Lower order address and data bus signals are multiplexed using this port. Pin 40 − This pin is used to provide power supply to the circuit. Print Page Previous Next Advertisements ”;

Microcontrollers – 8051 Interrupts ”; Previous Next Interrupts are the events that temporarily suspend the main program, pass the control to the external sources and execute their task. It then passes the control to the main program where it had left off. 8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI. Each interrupt can be enabled or disabled by setting bits of the IE register and the whole interrupt system can be disabled by clearing the EA bit of the same register. IE (Interrupt Enable) Register This register is responsible for enabling and disabling the interrupt. EA register is set to one for enabling interrupts and set to 0 for disabling the interrupts. Its bit sequence and their meanings are shown in the following figure. EA IE.7 It disables all interrupts. When EA = 0 no interrupt will be acknowledged and EA = 1 enables the interrupt individually. – IE.6 Reserved for future use. – IE.5 Reserved for future use. ES IE.4 Enables/disables serial port interrupt. ET1 IE.3 Enables/disables timer1 overflow interrupt. EX1 IE.2 Enables/disables external interrupt1. ET0 IE.1 Enables/disables timer0 overflow interrupt. EX0 IE.0 Enables/disables external interrupt0. IP (Interrupt Priority) Register We can change the priority levels of the interrupts by changing the corresponding bit in the Interrupt Priority (IP) register as shown in the following figure. A low priority interrupt can only be interrupted by the high priority interrupt, but not interrupted by another low priority interrupt. If two interrupts of different priority levels are received simultaneously, the request of higher priority level is served. If the requests of the same priority levels are received simultaneously, then the internal polling sequence determines which request is to be serviced. – IP.6 Reserved for future use. – IP.5 Reserved for future use. PS IP.4 It defines the serial port interrupt priority level. PT1 IP.3 It defines the timer interrupt of 1 priority. PX1 IP.2 It defines the external interrupt priority level. PT0 IP.1 It defines the timer0 interrupt priority level. PX0 IP.0 It defines the external interrupt of 0 priority level. TCON Register TCON register specifies the type of external interrupt to the microcontroller. Print Page Previous Next Advertisements ”;

Multiprocessor Configuration Overview ”; Previous Next Multiprocessor means a multiple set of processors that executes instructions simultaneously. There are three basic multiprocessor configurations. Coprocessor configuration Closely coupled configuration Loosely coupled configuration Coprocessor Configuration A Coprocessor is a specially designed circuit on microprocessor chip which can perform the same task very quickly, which the microprocessor performs. It reduces the work load of the main processor. The coprocessor shares the same memory, IO system, bus, control logic and clock generator. The coprocessor handles specialized tasks like mathematical calculations, graphical display on screen, etc. The 8086 and 8088 can perform most of the operations but their instruction set is not able to perform complex mathematical operations, so in these cases the microprocessor requires the math coprocessor like Intel 8087 math coprocessor, which can easily perform these operations very quickly. Block Diagram of Coprocessor Configuration How is the coprocessor and the processor connected? The coprocessor and the processor is connected via TEST, RQ-/GT- and QS0 & QS1 signals. The TEST signal is connected to BUSY pin of coprocessor and the remaining 3 pins are connected to the coprocessor’s 3 pins of the same name. TEST signal takes care of the coprocessor’s activity, i.e. the coprocessor is busy or idle. The RT-/GT-is used for bus arbitration. The coprocessor uses QS0 & QS1 to track the status of the queue of the host processor. Closely Coupled Configuration Closely coupled configuration is similar to the coprocessor configuration, i.e. both share the same memory, I/O system bus, control logic, and control generator with the host processor. However, the coprocessor and the host processor fetches and executes their own instructions. The system bus is controlled by the coprocessor and the host processor independently. Block Diagram of Closely Coupled Configuration How is the processor and the independent processor connected? Communication between the host and the independent processor is done through memory space. None of the instructions are used for communication, like WAIT, ESC, etc. The host processor manages the memory and wakes up the independent processor by sending commands to one of its ports. Then the independent processor accesses the memory to execute the task. After completion of the task, it sends an acknowledgement to the host processor by using the status signal or an interrupt request. Loosely Coupled Configuration Loosely coupled configuration consists of the number of modules of the microprocessor based systems, which are connected through a common system bus. Each module consists of their own clock generator, memory, I/O devices and are connected through a local bus. Block Diagram of Loosely Coupled Configuration Advantages Having more than one processor results in increased efficiency. Each of the processors have their own local bus to access the local memory/I/O devices. This makes it easy to achieve parallel processing. The system structure is flexible, i.e. the failure of one module doesn’t affect the whole system failure; faulty module can be replaced later. Print Page Previous Next Advertisements ”;

8085 Addressing Modes & Interrupts ”; Previous Next Now let us discuss the addressing modes in 8085 Microprocessor. Addressing Modes in 8085 These are the instructions used to transfer the data from one register to another register, from the memory to the register, and from the register to the memory without any alteration in the content. Addressing modes in 8085 is classified into 5 groups − Immediate addressing mode In this mode, the 8/16-bit data is specified in the instruction itself as one of its operand. For example: MVI K, 20F: means 20F is copied into register K. Register addressing mode In this mode, the data is copied from one register to another. For example: MOV K, B: means data in register B is copied to register K. Direct addressing mode In this mode, the data is directly copied from the given address to the register. For example: LDB 5000K: means the data at address 5000K is copied to register B. Indirect addressing mode In this mode, the data is transferred from one register to another by using the address pointed by the register. For example: MOV K, B: means data is transferred from the memory address pointed by the register to the register K. Implied addressing mode This mode doesn’t require any operand; the data is specified by the opcode itself. For example: CMP. Interrupts in 8085 Interrupts are the signals generated by the external devices to request the microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. Interrupt are classified into following groups based on their parameter − Vector interrupt − In this type of interrupt, the interrupt address is known to the processor. For example: RST7.5, RST6.5, RST5.5, TRAP. Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the processor so, the interrupt address needs to be sent externally by the device to perform interrupts. For example: INTR. Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some instructions into the program. For example: RST7.5, RST6.5, RST5.5. Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by writing some instructions into the program. For example: TRAP. Software interrupt − In this type of interrupt, the programmer has to add the instructions into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7. Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA. Note − NTA is not an interrupt, it is used by the microprocessor for sending acknowledgement. TRAP has the highest priority, then RST7.5 and so on. Interrupt Service Routine (ISR) A small program or a routine that when executed, services the corresponding interrupting source is called an ISR. TRAP It is a non-maskable interrupt, having the highest priority among all interrupts. Bydefault, it is enabled until it gets acknowledged. In case of failure, it executes as ISR and sends the data to backup memory. This interrupt transfers the control to the location 0024H. RST7.5 It is a maskable interrupt, having the second highest priority among all interrupts. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 003CH address. RST 6.5 It is a maskable interrupt, having the third highest priority among all interrupts. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 0034H address. RST 5.5 It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the PC register into the stack and branches to 002CH address. INTR It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by resetting the microprocessor. When INTR signal goes high, the following events can occur − The microprocessor checks the status of INTR signal during the execution of each instruction. When the INTR signal is high, then the microprocessor completes its current instruction and sends active low interrupt acknowledge signal. When instructions are received, then the microprocessor saves the address of the next instruction on stack and executes the received instruction. Print Page Previous Next Advertisements ”;

Microprocessor – 8086 Interrupts ”; Previous Next Interrupt is the method of creating a temporary halt during program execution and allows peripheral devices to access the microprocessor. The microprocessor responds to that interrupt with an ISR (Interrupt Service Routine), which is a short program to instruct the microprocessor on how to handle the interrupt. The following image shows the types of interrupts we have in a 8086 microprocessor − Hardware Interrupts Hardware interrupt is caused by any peripheral device by sending a signal through a specified pin to the microprocessor. The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin associated is INTA called interrupt acknowledge. NMI It is a single non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt request pin (INTR)and it is of type 2 interrupt. When this interrupt is activated, these actions take place − Completes the current instruction that is in progress. Pushes the Flag register values on to the stack. Pushes the CS (code segment) value and IP (instruction pointer) value of the return address on to the stack. IP is loaded from the contents of the word location 00008H. CS is loaded from the contents of the next word location 0000AH. Interrupt flag and trap flag are reset to 0. INTR The INTR is a maskable interrupt because the microprocessor will be interrupted only if interrupts are enabled using set interrupt flag instruction. It should not be enabled using clear interrupt Flag instruction. The INTR interrupt is activated by an I/O port. If the interrupt is enabled and NMI is disabled, then the microprocessor first completes the current execution and sends ‘0’ on INTA pin twice. The first ‘0’ means INTA informs the external device to get ready and during the second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable interrupt controller. These actions are taken by the microprocessor − First completes the current instruction. Activates INTA output and receives the interrupt type, say X. Flag register value, CS value of the return address and IP value of the return address are pushed on to the stack. IP value is loaded from the contents of word location X × 4 CS is loaded from the contents of the next word location. Interrupt flag and trap flag is reset to 0 Software Interrupts Some instructions are inserted at the desired position into the program to create interrupts. These interrupt instructions can be used to test the working of various interrupt handlers. It includes − INT- Interrupt instruction with type number It is 2-byte instruction. First byte provides the op-code and the second byte provides the interrupt type number. There are 256 interrupt types under this group. Its execution includes the following steps − Flag register value is pushed on to the stack. CS value of the return address and IP value of the return address are pushed on to the stack. IP is loaded from the contents of the word location ‘type number’ × 4 CS is loaded from the contents of the next word location. Interrupt Flag and Trap Flag are reset to 0 The starting address for type0 interrupt is 000000H, for type1 interrupt is 00004H similarly for type2 is 00008H and ……so on. The first five pointers are dedicated interrupt pointers. i.e. − TYPE 0 interrupt represents division by zero situation. TYPE 1 interrupt represents single-step execution during the debugging of a program. TYPE 2 interrupt represents non-maskable NMI interrupt. TYPE 3 interrupt represents break-point interrupt. TYPE 4 interrupt represents overflow interrupt. The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and interrupts from 32 to Type 255 are available for hardware and software interrupts. INT 3-Break Point Interrupt Instruction It is a 1-byte instruction having op-code is CCH. These instructions are inserted into the program so that when the processor reaches there, then it stops the normal execution of program and follows the break-point procedure. Its execution includes the following steps − Flag register value is pushed on to the stack. CS value of the return address and IP value of the return address are pushed on to the stack. IP is loaded from the contents of the word location 3×4 = 0000CH CS is loaded from the contents of the next word location. Interrupt Flag and Trap Flag are reset to 0 INTO – Interrupt on overflow instruction It is a 1-byte instruction and their mnemonic INTO. The op-code for this instruction is CEH. As the name suggests it is a conditional interrupt instruction, i.e. it is active only when the overflow flag is set to 1 and branches to the interrupt handler whose interrupt type number is 4. If the overflow flag is reset then, the execution continues to the next instruction. Its execution includes the following steps − Flag register values are pushed on to the stack. CS value of the return address and IP value of the return address are pushed on to the stack. IP is loaded from the contents of word location 4×4 = 00010H CS is loaded from the contents of the next word location. Interrupt flag and Trap flag are reset to 0 Print Page Previous Next Advertisements ”;

Microprocessor – 8085 Pin Configuration ”; Previous Next The following image depicts the pin diagram of 8085 Microprocessor − The pins of a 8085 microprocessor can be classified into seven groups − Address bus A15-A8, it carries the most significant 8-bits of memory/IO address. Data bus AD7-AD0, it carries the least significant 8-bit address and data bus. Control and status signals These signals are used to identify the nature of operation. There are 3 control signal and 3 status signals. Three control signals are RD, WR & ALE. RD − This signal indicates that the selected IO or memory device is to be read and is ready for accepting data available on the data bus. WR − This signal indicates that the data on the data bus is to be written into a selected memory or IO location. ALE − It is a positive going pulse generated when a new operation is started by the microprocessor. When the pulse goes high, it indicates address. When the pulse goes down it indicates data. Three status signals are IO/M, S0 & S1. IO/M This signal is used to differentiate between IO and Memory operations, i.e. when it is high indicates IO operation and when it is low then it indicates memory operation. S1 & S0 These signals are used to identify the type of current operation. Power supply There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply and VSS indicates ground signal. Clock signals There are 3 clock signals, i.e. X1, X2, CLK OUT. X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set frequency of the internal clock generator. This frequency is internally divided by 2. CLK OUT − This signal is used as the system clock for devices connected with the microprocessor. Interrupts & externally initiated signals Interrupts are the signals generated by external devices to request the microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. We will discuss interrupts in detail in interrupts section. INTA − It is an interrupt acknowledgment signal. RESET IN − This signal is used to reset the microprocessor by setting the program counter to zero. RESET OUT − This signal is used to reset all the connected devices when the microprocessor is reset. READY − This signal indicates that the device is ready to send or receive data. If READY is low, then the CPU has to wait for READY to go high. HOLD − This signal indicates that another master is requesting the use of the address and data buses. HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD request and it will relinquish the bus in the next clock cycle. HLDA is set to low after the HOLD signal is removed. Serial I/O signals There are 2 serial signals, i.e. SID and SOD and these signals are used for serial communication. SOD (Serial output data line) − The output SOD is set/reset as specified by the SIM instruction. SID (Serial input data line) − The data on this line is loaded into accumulator whenever a RIM instruction is executed. Print Page Previous Next Advertisements ”;