Category: digital-electronics

Digital to Analog Converter ”; Previous Next A Digital to Analog Converter (DAC) converts a digital input signal into an analog output signal. The digital signal is represented with a binary code, which is a combination of bits 0 and 1 while the analog signal is a continuous time function. This chapter deals with Digital to Analog Converters in detail. The block diagram of DAC is shown in the following figure − A Digital to Analog Converter (DAC) consists of a number of binary inputs and a single output. In general, the number of binary inputs of a DAC will be a power of two. Types of Digital to Analog Converters Depending on the construction and structure, there are two types of digital to analog converters, they are − Weighted Resistor DAC R-2R Ladder DAC The following sections discuss about these two types of DACs in detail. Weighted Resistor DAC A weighted resistor DAC produces an analog output, which is almost equal to the digital (binary) input by using binary weighted resistors in the inverting adder circuit. In short, a binary weighted resistor DAC is called as weighted resistor DAC. The circuit diagram of a 3-bit binary weighted resistor DAC is shown in the following figure − Recall that the bits of a binary number can have only one of the two values. i.e., either 0 or 1. Let the 3-bit binary input is b2b1b0. Here, the bits b2 and b0 denote the Most Significant Bit (MSB) and Least Significant Bit (LSB) respectively. The digital switches shown in the above figure will be connected to ground, when the corresponding input bits are equal to ”0”. Similarly, the digital switches shown in the above figure will be connected to the negative reference voltage, −VR when the corresponding input bits are equal to ”1”. In the above circuit, the non-inverting input terminal of an op-amp is connected to ground. That means zero volts is applied at the non-inverting input terminal of op-amp. According to the virtual short concept, the voltage at the inverting input terminal of op-amp is same as that of the voltage present at its non-inverting input terminal. So, the voltage at the inverting input terminal’s node will be zero volts. The nodal equation at the inverting input terminal’s node is − $$\mathrm{\frac{0 \: + \: V_{R}b_{2}}{2^{0}R} \: + \: \frac{0 \: + \: V_{R}b_{1}}{2^{1}R} \: + \: \frac{0 \: + \: V_{R}b_{0}}{2^{2}R} \: + \: \frac{0 \: – \: V_{0}}{R_{f}} \: = \: 0}$$ $$\mathrm{\Rightarrow \: \frac{V_{0}}{R_{f}} \: = \: \frac{V_{R}b_{2}}{2^{0}R} \: + \: \frac{V_{R}b_{1}}{2^{1}R} \: + \: \frac{V_{R}b_{0}}{2^{2}R}}$$ $$\mathrm{\Rightarrow \: V_{0} \: = \: \frac{V_{R}R_{f}}{R}(\frac{b_{2}}{2^{0}} \: + \: \frac{b_{1}}{2^{1}} \: + \: \frac{b_{0}}{2^{2}})}$$ Substituting, R = 2Rf in the above equation, $$\mathrm{V_{0} \: = \: \frac{V_{R}R_{f}}{2R_{f}}(\frac{b_{2}}{2^{0}} \: + \: \frac{b_{1}}{2^{1}} \: + \: \frac{b_{0}}{2^{2}})}$$ $$\mathrm{\therefore \: V_{0} \: = \: \frac{V_{R}}{2}(\frac{b_{2}}{2^{0}} \: + \: \frac{b_{1}}{2^{1}} \: + \: \frac{b_{0}}{2^{2}})}$$ The above equation represents the output voltage equation of a 3-bit binary weighted resistor DAC. Since the number of bits are three in the binary (digital) input, we will get seven possible values of output voltage by varying the binary input from 000 to 111 for a fixed reference voltage, VR. We can write the generalized output voltage equation of an N-bit binary weighted resistor DAC as shown below based on the output voltage equation of a 3-bit binary weighted resistor DAC. $$\mathrm{\therefore \: V_{0} \: = \: \frac{V_{R}}{2}(\frac{b_{N-1}}{2^{0}} \: + \: \frac{b_{N-2}}{2^{1}} \: + \dotso \: + \: \frac{b_{0}}{2^{N-1}})}$$ Disadvantages of Weighted Resistor DAC The disadvantages of the binary weighted resistor DAC are as follows − The difference between the resistance values corresponding to LSB & MSB will increase as the number of bits present in the digital input increases. It is difficult to design more accurate resistors as the number of bits present in the digital input increases. R-2R Ladder DAC The R-2R Ladder DAC overcomes the disadvantages of a binary weighted resistor DAC. As the name suggests, R-2R Ladder DAC produces an analog output, which is almost equal to the digital (binary) input by using a R-2R ladder network in the inverting adder circuit. The circuit diagram of a 3-bit R-2R Ladder DAC is shown in the following figure − Recall that the bits of a binary number can have only one of the two values. i.e., either 0 or 1. Let the 3-bit binary input is b2b1b0. Here, the bits b2 and b0 denote the Most Significant Bit (MSB) and Least Significant Bit (LSB) respectively. The digital switches shown in the above figure will be connected to ground, when the corresponding input bits are equal to ”0”. Similarly, the digital switches shown in above figure will be connected to the negative reference voltage, −VR when the corresponding input bits are equal to ”1”. It is difficult to get the generalized output voltage equation of a R-2R Ladder DAC. But we can find the analog output voltage values of R-2R Ladder DAC for individual binary input combinations easily. Advantages of R-2R Ladder DAC The advantages of a R-2R Ladder DAC are as follows − R-2R Ladder DAC contains only two values of resistor: R and 2R. So, it is easy to select and design more accurate resistors. If a greater number of bits are present in the digital input, then we have to include required number of R-2R sections additionally. Due to the above advantages, R-2R Ladder DAC is preferable over binary weighted resistor DAC. Important Parameters of DACs The following are some key parameters and factors that we must consider while selecting a digital to analog converter for a specific application − Resolution The number of

BCD to Excess-3 Converter ”; Previous Next A type of code converter in digital electronics that is used to convert a binary-coded decimal number into an equivalent excess-3 code is called a BCD to excess-3 converter. Hence, in the case of a BCD to excess-3 code converter, the input is an 8421 BCD code and the output is an XS-3 code. The following is the truth table of a BCD to excess-3 code converter − BCD Code Excess-3 Code B3 B2 B1 B0 X3 X2 X1 X0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 1 0 1 0 X X X X 1 0 1 1 X X X X 1 1 0 0 X X X X 1 1 0 1 X X X X 1 1 1 0 X X X X 1 1 1 1 X X X X Let us solve the truth table using the K-map to derive the Boolean expressions for the XS-3 output bits X0, X1, X2, and X3. K-Map for XS-3 Bit X0 The K-map simplification for the XS-3 bit X0 is shown in the following figure − On simplifying this K-map, we obtain the following Boolean expression, $$\mathrm{X_{0} \: = \: \overline{B_{0}}}$$ K-Map for XS-3 Bit X1 The K-map simplification for the XS-3 bit X1 is depicted below − This K-map simplification gives the following Boolean expression, $$\mathrm{X_{1} \: = \: \overline{B_{1}} \: \overline{B_{0}} \: + \: B_{1} \: B_{0}}$$ K-Map for XS-3 Bit X2 The K-map simplification for the XS-3 bit X2 is shown in the figure below. On simplifying this K-map, we obtain the following Boolean expression, $$\mathrm{X_{2} \: = \: B_{2} \: B_{1} \: + \: \overline{B_{2}} \: B_{0} \: + \: B_{2} \: \overline{B_{1}} \: \overline{B_{0}}}$$ K-Map for XS-3 Bit X3 The K-map simplification for the XS-3 bit X3 is depicted in the figure below − This K-map gives the following Boolean expression, $$\mathrm{X_{3} \: = \: B_{3} \: + \: B_{2} \: B_{1} \: + \: B_{2} \: B_{0}}$$ The logic circuit diagram of the BCD to XS-3 converter is shown in the following figure − This circuit converters a 4-bit BCD code into an equivalent XS-3 code. Print Page Previous Next Advertisements ”;

Implementation of NOR Gate from NAND Gate ”; Previous Next NOR and NAND gates are universal logic gates, using which we can implement any logic gate or any other logical expression. Read this tutorial to find out how you can implement a NOR gate using a NAND gate. What is a NOR Gate? NOR Gate is a type of universal logic gate, because this logic gate can be used for implementation of any other type of logic gate. NOR means “NOT + OR”. That means the OR output is NOTed or inverted. Therefore, the NOR gate is a combination of OR gate and a NOT gate. $$\mathrm{NOR \: Gate \: = \: OR \: Gate \:+ \: NOT \: Gate}$$ A NOR gate is a type of logic gate whose output is HIGH (Logic 1), only when all its inputs are LOW (Logic 0), and it gives an output LOW (Logic 0), even if any of its inputs become HIGH (Logic 1). The logic symbol of a two input NOR gate is shown in Figure-1. Output Equation of NOR Gate If A and B are the input variables and Y is the output variable of the NOR gate, then the output of the NOR gate is given by, $$\mathrm{Y \: = \: \overline{A \: + \: B} \: = \: (A \: + \: B)”}$$ It is read as “Y is equal to A plus B whole bar”. Truth Table of NOR Gate The table that shows the relationship between inputs and output of a logic gate is referred to as a truth table. The following is the truth table of the NOR gate − Input Output A B Y = (A + B)” 0 0 1 0 1 0 1 0 0 1 1 0 What is a NAND Gate? The NAND Gate is a type of universal logic gate. Where, a universal logic gate is one that can be used to realize any kind logical expression or any other type of logic gate. A NAND gate is basically a combination of two basic logic gates namely AND gate and NOT gate, i.e., $$\mathrm{NAND \: Logic \: = \: AND \: Logic \: = \: NOT \: Logic}$$ A NAND gate is the type of logic gate whose output is LOW (Logic 0) when all its inputs are high, and its output is HIGH (Logic 1), when any of its inputs is LOW (Logic 0). Therefore, the operation of the NAND gate is opposite that of the AND gate. The logic symbol of a two input NAND gate is shown in Figure-2. Output Equation of NAND Gate If A and B are the input variables and Y is the output variable of the NAND gate, then its output is given by, $$\mathrm{Y \: = \: \overline{A \: \cdot \: B} \: = \: (A \: + \: B)”}$$ It is read as “Y is equal to A.B whole bar”. Truth Table of NAND Gate The following is the truth table of the NAND gate − Input Output A B Y = (A·B)” 0 0 1 0 1 1 1 0 1 1 1 0 Now, let us discuss the implementation of NOR Gate from NAND Gate. Implementation of NOR Gate from NAND Gate As mentioned above, the NAND gate is a universal logic gate, therefore, it can be used to realize the any other logic gate. The implementation of NOR gate using the NAND gate is shown in Figure-3. From the logic circuit, it is clear that for the implementation of NOR gate using NAND gates only, we require 4 NAND gates. The first two NAND gates perform the complement of input variables A and B, the third NAND gate produce the NAND output of the complemented inputs, i.e. A” and B”. Finally, the fourth NAND gate again operates as an inverter and produce the output Y. This output Y is the equivalent to the output of the NOR gate. Output Equation The output of the first and second NAND gates is, $$\mathrm{Y_{1} \: = \: \bar{A} \:\: and \:\: Y_{2} \: = \: \bar{B}}$$ The output of the third NAND gates is, $$\mathrm{Y_{3} \: = \: \overline{\bar{A} \: \cdot \: \bar{B}} \: = \: A \: + \: B}$$ The output of the fourth NAND gate is, $$\mathrm{Y \: = \: \overline{A \: + \: B}}$$ Hence, this is the output of a NOR Gate. In this way, we can implement a NOR gate using NAND gates only. Print Page Previous Next Advertisements ”;

Digital Electronics – Encoders ”; Previous Next An encoder is a combinational logic circuit that is used to convert a normal or familiar information into a coded format. In other words, an encoder is a digital device that coverts a piece of information represented in the form of decimal digits and alphabetic characters into a coded form like binary representation. The operation that the encoder performs is termed as encoding. In this chapter, we will explain the basics of encoder and commonly used types of encoders. What is an Encoder? An encoder is a digital combinational circuit that converts a human friendly information into a coded format for processing using machines. In simple words, an encoder converts a piece of information normal form to coded form. This process is called encoding. Encoders are crucial components in various digital electronics applications such as data transmission, controlling and automation, communication, signal processing, etc. An encoder consists of a certain number of input and output lines. Where, an encoder can have maximum of “2n” input lines whereas “n” output lines. Hence, an encoder encodes information represented by “2n” input lines with “n” bits. The block diagram of an encoder is shown in the following figure − Let us now discuss different types of encoders commonly used in digital electronic applications. Types of Encoders Some of the commonly used types of encoders in digital electronics − 4 to 2 Encoder 8 to 3 Encoder (Octal Encoder) Decimal to BCD Encoder Let us now discuss these three types of most commonly used encoders in detail. 4 to 2 Encoder A 4 to 2 Encoder is a type of encoder which has 4 (22) input lines and 2 output lines. It produces an output code (i.e., convert input information in a 2-bit format) depending on the combination of input lines. The block diagram of a 4 to 2 Encoder is shown in the following figure. The working of a 4 to 2 Encoder for different input combinations is described in the following truth table − Inputs Outputs I3 I2 I1 I0 Y1 Y0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 From this truth table, we can derive the Boolean expression for each output of the 4 to 2 Encoder as follows − $$\mathrm{Y_{0} \: = \: I_{1} \: + \: I_{3}}$$ $$\mathrm{Y_{1} \: = \: I_{2} \: + \: I_{3}}$$ It is clear that we can implement the logic circuit of the 4 to 2 Encoder using two OR gates. The following figure depicts the logic diagram of the 4 to 2 Encoder. Applications of 4 to 2 Encoder The 4 to 2 Encoder is widely used in the following applications: Data multiplexing, Generating digital control signals, Address decoding applications, Encoding data in digital systems, etc. Octal to Binary Encoder The octal to binary encoder is a type of encoder that converts an octal code into binary code. It accepts 8 input lines and produces a 3-bit output depending on the combination of input lines. Therefore, it is also known as 8 to 3 Encoder. The block diagram of an octal to binary encoder is shown in the following figure − The following truth table describes the working of an octal to binary encoder − Inputs Outputs I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 From this truth table, we can write the Boolean expression for the outputs of the octal to binary encoder as follows. $$\mathrm{Y_{0} \: = \: I_{1} \: + \: I_{3} \: + \: I_{5} \: + \: I_{7}}$$ $$\mathrm{Y_{1} \: = \: I_{2} \: + \: I_{3} \: + \: I_{6} \: + \: I_{7}}$$ $$\mathrm{Y_{2} \: = \: I_{4} \: + \: I_{5} \: + \: I_{6} \: + \: I_{7}}$$ From these expressions, it is clear that the implementation of an octal to binary encoder requires 3 OR gates. The logic circuit diagram of the octal to binary encoder is shown in the following figure − Applications of Octal to Binary Encoder The octal to binary encoder is used

Arithmetic Logic Unit in Digital Electronics ”; Previous Next The Arithmetic Logic Unit (ALU) is the fundamental component in a computing system like a computer. It is basically the actual data processing element within the central processing unit (CPU) in a computing system. It performs all the arithmetic and logical operations and forms the backbone of modern computer technology. In this chapter, we will explain the working of the arithmetic logic unit, along with its main components, their functions, and the importance of the ALU in the field of digital system designs. What is Arithmetic Logic Unit? Arithmetic Logic Unit abbreviated as ALU is considered as the engine or heart of every central processing unit (CPU). ALU is basically a combination logic circuit that can perform arithmetic and logical operation on digital data (data in binary format). It can also execute instructions given to a computing system like a digital computer. Within the complex architecture of a digital computing system, the arithmetic logic unit or ALU plays an important role as it executes and processes all the instructions, performs calculations, manipulates binary data, and performs various decision-making operations. The development of arithmetic logic unit begins with the need for efficient, high speed, and accurate data processing and computation. With the advancement in electronics technologies, ALU has become a highly sophisticated digital data processing device that can handle a large number of complex instructions and computational tasks. Today’s ALU provides high accuracy, precision, and significantly fast processing speed in computing operations. Features of Arithmetic Logic Unit Here are some key features of arithmetic logic unit − The ALU can perform all arithmetic and logic operations such as addition, subtraction, multiplication, division, logical comparisons, etc. It can also perform bitwise and mathematical operations on binary numbers. It contains two segments namely, AU (arithmetic unit) and LU (logic unit) to perform arithmetic operations and logical operations respectively. It is the computational powerhouse within a central processing unit (CPU). ALU is the part of every CPU where actual data processing takes place. ALU is responsible for interpreting the code instructions based on which operations to be performed on the input data. Once the data processing is completed, the ALU sends the outcomes to the memory unit or output unit. Main Components of Arithmetic Logic Unit The arithmetic logic unit consists of various functional parts that are responsible for performing specific operations like addition, subtraction, multiplication, division, comparison, and more. Some of the key components of the arithmetic logic unit are explained below − Arithmetic Unit The main components used in the arithmetic unit (AU) segment of the arithmetic logic unit are as follows − Adder The adder or binary adder is one of the important components of the arithmetic logic unit. It performs the addition of two or more binary numbers. To accomplish this operation, it performs a series of logical and arithmetic operations. Some common types of adders used in the arithmetic ogic unit are half-adder, full-adder, parallel adder, and ripple carry adder. Each type of adder is designed and optimized to perform a specific computing operation. Subtractor The subtractor is another digital combinational circuit designed to perform subtraction of binary numbers. In most arithmetic logic unit, the subtractor uses 2’s complement arithmetic to perform subtraction on binary numbers. Multiplier and Divider In more complex and advanced arithmetic logic units, dedicated multiplier and divider circuits are also implemented to perform multiplication and division on binary numbers. These circuits use advanced processing techniques like iterative or parallel processing to accomplish these operations. Logic Unit The logic unit (LU) of the ALU comprises the components responsible for performing Boolean or comparison operations. The following are some main components of the logic unit of an ALU − Logic Gates The logic gates like AND, OR, NOT, NAND, NOR, XOR, and XNOR are the key components of logic unit. These are standard logic circuits that can manipulate input data based on some predefined logical instructions and generate a desired output. Each logic gate can perform a specific logical operation. However, different types of logic gates can be connected together in a specific manner to perform complex logical operations. Type of Logic Gate The brief overview of each type of logic gate is explained here − AND Gate − It performs the Boolean multiplication on input binary data. Its output is logic 1 or true, only when all its inputs are logic 1 or true. OR Gate − The OR gate performs the Boolean addition of input binary data. It generates a logic 1 or true output, if any of its inputs is logic 1 or true. NOR Gate − The NOT gate performs the inversion operation. It gives a logic 1 or true output when its input is logic 0 or false and vice-versa. NAND Gate − The NAND gate performs the NOTed AND operation and produces a logic 1 or true output when both inputs or any of the inputs is logic 0 or false. NOR Gate − The NOR gate performs the NOTed OR operation and generates a logic 1 or true output when all its inputs are logic 0 or false. XOR Gate − The XOR gate performs the exclusive OR operation and produces a logic 1 or true output when its both inputs are dissimilar. Hence, it is used as inequality detector. XNOR Gate − The XNOR gate performs the exclusive NOR operation and gives a logic 1 or true output when both its inputs are similar. Thus, it is used as an equality detector. This is all about structure and components of the arithmetic logic unit. Let us now understand what functions an ALU can perform. Functions of Arithmetic

Half Subtractor using NAND Gates ”; Previous Next In digital electronics, a subtractor is a combinational logic circuit that performs the subtraction of two binary numbers. However, the subtraction of binary number can be performed using adder circuits by taking 1’s or 2’s compliments. But, we may also realize a dedicate circuit to perform the subtraction of two binary numbers. In the subtraction of two binary numbers, each subtrahend bit of the number is subtracted from its corresponding significant minuend bit to form a difference bit. During the subtraction, if the minuend bit is smaller than the subtrahend bit, then a 1 is borrowed from the next position. Depending upon the number of bits taken as input, there are two types of subtractors namely, Half Subtractor and Full Subtractor. A half subtractor is one which takes two binary digits as input and gives a difference bit and a borrow bit (if any) as output. On the other hand, a full subtractor is one that takes three bits as input, i.e. two are the input bits and one is the input borrow bit from the previous stage, and gives a difference bit and a output borrow bit as the output. Since a subtractor is a combinational logic circuit, i.e. it is made of logic gates. We can realize a full adder circuit using different types of logic gates like AND, OR, NOT, NAND, NOR, etc. Here, we will discuss the implementation of a half subtractor using NAND gates. But before that let’s have a look into the basics of the half subtractor. What is Half Subtractor? A half-subtractor is a combinational circuit which has two inputs and two outputs where one output is difference and another is borrow bit. The half subtractor produces the difference between the two binary bits at the input and also produces a borrow output (if any). In the subtraction (A-B), A is called as Minuend bit and B is called as Subtrahend bit. The block diagram of the half subtractor is shown in Figure-1. Here, A and B are the input variables (binary digits) and d is the output difference bit and b is the borrow bit. We can understand the operation of a half subtractor with the help of its truth table. Truth Table of Half Subtractor The following is the truth table the half subtractor − Inputs Outputs A B D (Difference) B (Borrow) 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 Using this truth table, we can determine the output equation of the half subtractor. The following are the equations of difference bit (d) and borrow bit (b) − Different Bit (D) − $$\mathrm{Difference, \: d \: = \: A”B \: + \: AB” \: = \: A \oplus B}$$ Borrow Bit (B) $$\mathrm{Borrow, \: b \: = \: A”B}$$ Now, let us discuss the realization of half subtractor using NAND gates. Half Subtractor Using NAND Gates We may implement the logic circuit of half subtractor using NAND gates only as shown in figure-2. From this logic circuit diagram, we can see that 9 NAND gates are required for realization of the half subtractor. The output equations of the half subtractor in NAND logic are as follows − Difference Bit (D) $$\mathrm{Difference, \: d \: = \: \overline{\overline{A \cdot \: \overline{AB}} \: \cdot \: \overline{B \cdot \overline{AB}}} \ = \: A \oplus B}$$ Borrow Bit (B) $$\mathrm{Borrow, \: b \: = \: \overline{\overline{B \cdot \: \overline{AB}}} \: = \: \overline{A} \: B}$$ In this way, we can realize the half subtractor using the NAND gates only. Print Page Previous Next Advertisements ”;

Implementation of a Full Subtractor using Two Half Subtractors ”; Previous Next A subtractor is a combinational logic circuit that can perform the subtraction of two numbers (or binary numbers) and produce the difference between them. It is a combinational logic circuit. Therefore, the output of the subtractor depends only on its present inputs. There are two types of subtractors namely, Half Subtractor Full Subtractor Read this tutorial to find out how you can realize a full subtractor using half subtractors. For the implementation of a full subtractor, we require two half subtractors. Let”s start with a brief overview of half and full subtractors. What is a Half Subtractor? A half-subtractor is a combinational logic circuit that has two inputs and two outputs where one output is difference bit (d) and another is the borrow bit (b). The half subtractor produces the difference between the two binary bits and also produces a borrow output (if any). In the subtraction (A-B), A is called Minuend and B is called Subtrahend bit. The block diagram and logic circuit diagram of the half subtractor are shown in Figure-1. From the logic diagram of the half subtractor, it can be seen that a half subtractor can be realized using an XOR gate together with a NOT gate and an AND gate. The difference bit (d) of the half subtractor is given by XORing the two inputs A and B. Therefore, $$\mathbf{Difference,\: d \: = \: A \oplus B \: = \: A”B \: + \: AB”}$$ The borrow (b) of the half subtractor is the AND of A” (compliment of A) and B. Therefore, $$\mathbf{Borrow, \: b \: = \: A”B}$$ What is a Full Subtractor? A full subtractor is also a combinational logic circuit which has three inputs A, B, bin and two outputs “d” and “b”. Where, “A” is the minuend bit, “B” is the subtrahend bit, “bin” is borrow produced at the previous stage, d is the output difference bit and b is the output borrow bit. The block diagram and circuit diagram of a full-subtractor is shown in Figure-2. From the logic diagram of the full subtractor, we can see that the implementation of a fullsubtractor requires two XOR gates, two NOT gates, two AND gates, and one OR gate. Now, let us discuss the realization of full subtractor using two half subtractors. Implementation of a Full Subtractor using Two Half Subtractors A full subtractor can be realized using two half subtractors. It will take two half-subtractors and one OR gate. The logic circuit diagram of the full subtractor using two half subtractors is shown in Figure-3. The first half subtractor performs XOR operation on input bits A and B, and AND operation on A” and B to produce an intermediate borrow bit The second half subtractor performs the XOR operation on the output of first XOR gate and the input borrow bit (bin), and the AND gate of the second half circuit gives an output equal to (A”B + AB”)”.bin. The output of the second XOR gate is the output different bit (d), and the output borrow bit (b) is obtained by ORing the outputs of two AND gates. In this way, we can realize a full subtractor by cascading two half subtractors, as shown in the above figure Print Page Previous Next Advertisements ”;

Digital Electronics – Latches ”; Previous Next A latch is an asynchronous sequential circuit whose output changes immediately with the change in the applied input. A latch is used to store 1 bit information in a digital system, so it is considered as the most elementary memory element. In this chapter, we will explain in detail about latches in digital electronics along with their types and applications. What is a Latch? In digital electronics, a latch is an asynchronous sequential circuit that can store 1-bit information. It is used as the fundamental memory element in digital circuits. A latch can have two stable states namely, set and reset. The set state is denoted by the logic 1 and the reset state is represented by the logic 0. Due to these two stable states, a latch is also known as a bistable-multivibrator. The state of a latch toggles according to the applied input. The most important thing to be noted about latches is that they do not have a clock signal for synchronization. That is why they are called asynchronous sequential circuits. The logic gates are the fundamental building blocks of latches. Since there is no synchronization and clock signal used. Hence, the latches operate immediately on the application of input signals. Characteristics of Latches Some key characteristics of latches are explained below − Latches can store 1-bit of digital information that can be represented using either logic 0 or logic 1. Thus, the latches are mainly used as memory elements in digital circuits. Latches have a feedback mechanism that allows them to maintain their current state as it is until the next input is applied. The operation of latches is completely controlled by applied inputs that means the output of the latches updates based on the change in the input signals. Types of Latches The following are the main types of latches that used in digital circuits and systems − SR Latch JK Latch D Latch T Latch Let us now discuss about each type of latch in detail. SR Latch The SR latch is a type of latch which has two input lines designated as S and R. Where, S represents the Set input and R represents the Reset input. Thus, it is also known as Set-Reset Latch. The SR latch has two stable states namely Set state (S) and Reset state (R). The block diagram of the SR latch is shown in the following figure. In the case of SR latch, the S input sets the output Q to 1 and Q” to 0. On the other hand, the R input sets the output Q to 0 and Q” to 1. In case, when both S and R inputs are high, the latch is said to be in forbidden state. The complete operation of the SR latch for different input combinations is described in the following truth table − Inputs Outputs Comment S R Q Q” 0 0 Q Q” No change 0 1 0 1 Reset state 1 0 1 0 Set state 1 1 X X Forbidden state The SR latch can be implemented by connecting two NOR gates in a cross-coupled manner as shown in the following figure. JK Latch The JK latch is another type of latch which has two inputs namely, J and K. Here, the input J is similar to S input and the input K is similar to R input in an SR latch. The operation of the JK latch is similar to that of the SR latch but it does not have the forbidden state. Instead, it has a toggle state in which the outputs Q and Q” swap their states when both inputs J and K are 1. Therefor, the JK latch is mainly designed to overcome the problem of forbidden state in the SR latch. The block diagram of the JK latch is shown in the following figure − The truth table given below describes the operation of the JK latch for different input combinations − Inputs Outputs Comment J K Q Q” 0 0 Q Q” No change 0 1 0 1 Reset state 1 0 1 0 Set state 1 1 Q” Q Toggle state From this truth table, it is clear that the problem of forbidden state is addressed by implementing the toggle state. The logic circuit of the JK latch consists of a combination of two NOR gates and two AND gates as shown in the following figure. D Latch The D Latch, also known as Data latch or transparent latch, is a type of bistable multivibrator which has two input signals namely, D (Data) input and E (Enable) input. The output Q of the D latch is same as the input applied at the D input line as long as the E input is high. When the E input goes low, the output of the D latch is held as it is until the new input is applied to the D input. The block diagram of the D latch is shown in the following figure. The truth table given below explains the operation of the D latch − Inputs

3 Variable K-Map in Digital Electronics ”; Previous Next A K-Map or Karnaugh Map is a graphical method that used for simplifying the complex algebraic expressions in Boolean functions. This method avoid the use of complex theorems and equations manipulations. A K-Map is basically a special form of a truth table that can easily map out the values of parameters and gives a simplified Boolean expression. K-Map method is best suited for such Boolean functions that have two to four variables. However, it can be used for Boolean functions having five or six variables as well, but its process becomes more difficult with the increased number of variables in the function. Therefore, in practice, we mostly use Two-Variable K-Map, Three-Variable K-Map, and Four-Variable K-Map. But, sometimes, the Five-Variable K-Map and Six-Variable K-Map are also used to derive the Boolean expressions. Here, we will discuss the 3 Variable K-Map and its application to simplify a complex Boolean function. Three-Variable K-Map We can use the K-Map to simplify a Boolean function of three-variables. A Boolean function in three variables (A, B, C) can be expressed in the standard sum of product (SOP) form that can have total eight possible combinations, which are as follows − $$\mathrm{(A”B”C”), (A”B”C), (A”BC”), (A”BC), (AB”C”), (AB”C), (ABC”), (ABC)}$$ We can designate each of these combinations by m0, m1, m2, m3, m4, m5, m6, and m7 respectively. Each of these terms are called a min-term. In these combinations, A is called MSB (Most Significant Bit) and C is called LSB (Least Significant Bit). In terms of POS (Product of Sum) form, the eight possible combinations of the three variables Boolean expression are as follows − $$\mathrm{(A+B+C), (A+B+C”), (A+B”+C), (A+B”+C”), (A”+B+C), (A”+B+C”), (A”+B”+C), (A”+B”+C”)}$$ Each one of these combinations are often designated by M0, M1, M2, M3, M4, M5, M6, and M7 respectively. Each of these terms is called a maxterm. Similar to the minterm, A is called MSB (Most Significant Bit) and C is called LSB (Least Significant Bit). Therefore, a three variable K-Map has eight (23) squares or cells, and each square on the K-Map represents a minterm of a maxterm as shown in the following figure. Here, the small number on the bottom right corner of each cell indicates the minterm or maxterm designation. The binary numbers along the top of the K-Map indicates the condition of variables B and C for each column. The binary number along the left side of the map against each row represents the condition of the variable A for that row. For example, the binary number of 10 on the top of the fourth column in the above figure indicates that the variable B appears in non-complimented form and the variable C appears in complimented form in all the minterms in that column. The binary number 0 on the left of the first row on the K-map indicates that the variable A appears in its complimented form in all the minterms, and the binary number 1 on the left of the second row on the K-Map indicates that the variable A appears in its non-complimented form in all the minterms. Also, note that the binary numbers on top of the K-map are not in the normal binary order, but they are actually in the Gray code. The use of Gray code in K-map ensures that the two physically adjacent cells are actually adjacent which means their minterms or maxterms differs by one variable only. Numerical Example Map the following three-variable Boolean expression on K-Map. $$\mathrm{f \: = \: \overline{A} \: \overline{B} \: C \: + \: A \: \overline{B} \: C \: + \: \overline{A} \: B \: \overline{C} \: + \: A \: \overline{B} \: \overline{C} \: + \: A \: B \: C}$$ Solution In the given Boolean expression, the minterms are − $$\mathrm{\overline{A} \: \overline{B} \: C \: = \: 001; \: A \: \overline{B} \: C \: = \: 101; \: \overline{A} \: B \: \overline{C} \: = \: 010; \: A \: \overline{B} \: \overline{C} \: = \: 100; \: ABC \: = \: 111}$$ Therefore, $$\mathrm{m_{1} \: = \: \overline{A} \: \overline{B} \: C \: = \: 001}$$ $$\mathrm{m_{5} \: = \: A \: \overline{B} \: C \: = \: 101}$$ $$\mathrm{m_{2} \: = \: \overline{A} \: B \: \overline{C} \: = \: 010}$$ $$\mathrm{m_{4} \: = \: A \: \overline{B} \: \overline{C} \: = \: 100}$$ $$\mathrm{m_{7} \: = \: ABC \: = \: 111}$$ Hence, the expression is given by, $$\mathrm{f \: = \: \sum \: m (1, \: 5, \: 2, \: 4, \: 7)}$$ The K-map of this expression is shown in the following figure − Conclusion From the above discussion, we may conclude that the three variable K-Map is a graphical method used to simplify the complex three variable Boolean function. A three-variable Kmap has eight squares or cells. Print Page Previous Next Advertisements ”;

Digital Electronics – DeMorgan”s Theorem ”; Previous Next In Boolean algebra, several rules are defined to perform operations in digital logic circuits. Boolean algebra is a tool to perform operation on binary digits, i.e. 0 and 1. These two binary digits 0 and 1 are used to denote FALSE and TRUE states of a digital circuit at input and output ends. Boolean algebra, developed by George Boole, uses 0s and 1s to create truth tables and logic expressions of digital circuits like AND, OR, NOT, etc. which are used to analyze and simplify the complex circuits. There were another English mathematician Augustus DeMorgan who explained the NAND and NOR operations as NOT AND and NOT OR operations respectively. This explanation was named De Morgan”s Theorem. In this tutorial, we will discuss the DeMorgan”s theorem in detail. What is DeMorgan”s Theorem? DeMorgan”s Theorem is a powerful theorem in Boolean algebra which has a set of two rules or laws. These two laws were developed to show the relationship between two variable AND, OR, and NOT operations. These two rules enable the variables to be negated, i.e. opposite of their original form. Therefore, DeMorgan”s theorem gives the dual of a logic function. Now, let us discuss the two laws of DeMorgan”s theorem. DeMorgan”s First Theorem (Law 1) DeMorgan”s First Law states that the complement of a sum (ORing) of variables is equal to the product (ANDing) of their individual complements. In other words, the complement of two or more ORed variables is equivalent to the AND of the complements of each of the individual variables, i.e. $$\mathrm{\overline{A+B} \: = \: \bar{A} cdot \bar{B}}$$ Or, it may also be represented as, $$\mathrm{\lgroup A \: + \: B \rgroup” \: = \: A”cdot B”}$$ The logic implementation of left side and right side of this law is shown in Figure 1. Thus, DeMorgan”s first law proves that the NOR gate is equivalent to a bubbled AND gate. The following truth table shows the proof of this law. Left Side Right Side Input Output Input Output A B (A + B)” A” B” A”· B” 0 0 1 1 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 0 This truth table proves that the Boolean expression on the left is equivalent to that on the right side of the expression of DeMorgan”s first law. Also, the first law of DeMorgan”s theorem can be extended to any number of variables, or a combination of variables. For example, $$\mathrm{\overline{A \: + \: B \: + \: C \: + \: D \: + \: E \: + \: \dotso} \: = \: \bar{A} \: \bar{B} \: \bar{C} \: \bar{D} \: \bar{E} \: \dotso}$$ Also, $$\mathrm{\overline{ABC \: + \: DE \: + \: FGH \: + \: \dotso}\: = \: \overline{\lgroup ABC \rgroup}.\overline{\lgroup DE \rgroup}.\overline{\lgroup FGH\rgroup}.\dotso}$$ From the above discussion, we may conclude that the DeMorgan”s First Law converts an expression from a sum form under a NOT sign to a product form. DeMorgan”s Second Theorem (Law 2) DeMorgan”s second law states that the complement of the product (ANDing) of variables is equivalent to the sum (ORing) of their individual complements. In other words, the complement of two or more ANDed variables is equal to the sum of the complement of each of the individual variables, i.e., $$\mathrm{\overline{AB} \: = \: \overline{A} \: + \: \overline{B}}$$ It may also be represented as, $$\mathrm{\lgroup AB \rgroup” \: = \: A” \: + \: B”}$$ The logic implementation of left and right sides of this expression is shown in Figure 2. Hence, DeMorgan”s second law proves that the NAND gate is equivalent to a bubbled OR gate. The following truth table shows the proof of this law. Left Side Right Side Input Output Input Output A B AB A” B” A” + B” 0 0 0 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 This truth table proves that the Boolean expression on the left side is equivalent to that on the right side of the expression of DeMorgan”s second law. Similar to the first law, we may extend the DeMorgan”s second law for any number of variables or combination of variables. For example, $$\mathrm{\overline{ABCDE \dotso} \: = \: \overline{A} \: + \: \overline{B} \: + \: \overline{C} \: + \: \overline{D} \: + \: \overline{E} \: + \: \dotso}$$ And, for a combination of variables, $$\mathrm{\overline{\lgroup ABC \rgroup} \overline{\lgroup DE \rgroup} \overline{\lgroup FG \rgroup \dotso} \: = \: \overline{ABC} \: + \: \overline{DE} \: + \: \overline{FG}}$$ Hence, from the above discussion, we can conclude that DeMorgan”s second law transforms a product form of variables or combination of variables under a NOT sign into a sum form. Therefore, DeMorgan”s laws transforms an AND operation into an OR operation, and an OR operation into an AND operation. This principle is called duality. Example 1 Apply DeMorgan”s theorem to the following Boolean expression, $$\mathrm{F \: = \: \overline{AB \overline{ \lgroup C \: +