Category: digital-electronics

Programmable Logic Devices ”; Previous Next Programmable Logic Devices (PLDs) are a collection of integrated circuits which are configured to perform various logical functions. PLDs play an important role in the field of engineering and technology, as they form the basis of innovation and support engineers to develop automated digital systems to improve process flexibility and efficiency. Here, “programmable” means defining a function that can be performed multiple times without human intervention. Programmable Logic Devices (PLDs) are the integrated circuits. They contain an array of AND gates & another array of OR gates. There are three kinds of PLDs based on the type of array(s), which has programmable feature. Programmable Read Only Memory Programmable Array Logic Programmable Logic Array The process of entering the information into these devices is known as programming. Basically, users can program these devices or ICs electrically in order to implement the Boolean functions based on the requirement. Here, the term programming refers to hardware programming but not software programming. In this chapter, we will explain the basic concepts of programmable logic devices, their types, advantages, limitations, and applications. Programmable Read Only Memory (PROM) Read Only Memory (ROM) is a memory device, which stores the binary information permanently. That means, we can’t change that stored information by any means later. If the ROM has programmable feature, then it is called as Programmable ROM (PROM). The user has the flexibility to program the binary information electrically once by using PROM programmer. PROM is a programmable logic device that has fixed AND array & Programmable OR array. The block diagram of PROM is shown in the following figure. Here, the inputs of AND gates are not of programmable type. So, we have to generate 2n product terms by using 2n AND gates having n inputs each. We can implement these product terms by using nx2n decoder. So, this decoder generates ‘n’ min terms. Here, the inputs of OR gates are programmable. That means, we can program any number of required product terms, since all the outputs of AND gates are applied as inputs to each OR gate. Therefore, the outputs of PROM will be in the form of sum of min terms. Example Let us implement the following Boolean functions using PROM. $$\mathrm{A(X,Y,Z):=:sum mleft ( 5,6,7 right )}$$ $$\mathrm{B(X,Y,Z):=:sum mleft ( 3,5,6,7 right )}$$ The given two functions are in sum of min terms form and each function is having three variables X, Y & Z. So, we require a 3 to 8 decoder and two programmable OR gates for producing these two functions. The corresponding PROM is shown in the following figure. Here, 3 to 8 decoder generates eight min terms. The two programmable OR gates have the access of all these min terms. But, only the required min terms are programmed in order to produce the respective Boolean functions by each OR gate. The symbol ‘X’ is used for programmable connections. What is a Programmable Logic Device? A Programmable Logic Device (PLD) can be defined as an integrated circuit (IC) which can be programmed to perform specific functions. Here, programming means we can define a set of instructions that can be executed to perform the functions multiple times without need of any human intervention. The primary need of developing PLDs is occurred to implement digital logic functions that can copy the behavior of conventional logic circuits and replicate it many times. However, the PLDs are different from normal digital logic circuits in terms of programmability, which means we can define the desired logic functions by setting a collection of instructions in the device. Types of PLDs Based on the type of device used, Programmable Logic Devices (PLDs) can be classified into the following two types − Bipolar PLDs CMOS PLDs Let us discuss each type of programmable logic device in detail. Bipolar PLDs Bipolar PLDs are the types of programmable logic devices in which Bipolar Junction Transistor (BJT) is the main functional device. Bipolar PLDs are the older versions of programmable logic devices. Thus, they were commonly used before the development of CMOS PLDs. The following are some important characteristics of the bipolar programmable logic devices − Bipolar PLDs provide fast switching speeds and hence they can operate at higher frequencies. Bipolar PLDs are better suited for applications involving rapid signal processing and require fast response times. Bipolar PLDs require more power to operate. Bipolar PLDs have better immunity to electronic noise and interference. All these characteristics make the bipolar programmable logic devices well-suited to use in the applications where high-speed operation and reliability are critical, such as aerospace, military, and telecommunications systems. CMOS PLDs CMOS PLDs stand for Complementary Metal Oxide Semiconductor Programmable Logic Devices. As their name implies, CMOS PLDs use the CMOS transistors i.e., NMOS (N-channel Metal Oxide Semiconductor) and PMOS (P-channel Metal Oxide Semiconductor) transistors as the fundamental component. CMOS PLDs are basically the modern versions of PLDs and are widely used in modern digital systems due to their numerous advantages. Some important characteristics of CMOS PLDs are described below − CMOS PLDs require very less amount of power to operate. Hence, this characteristic makes the CMOS PLDs well-suited to use in battery-power devices where energy efficiency is an important factor. CMOS PLDs are more reliable and robust. As they are designed to withstand against various environmental factors like high/low temperatures, voltage fluctuations, and different radiation interferences. CMOS PLDs are also excellent in terms of scalability. CMOS PLDs are newer PLD devices and hence are very commonly used in various modern electronics devices like consumer electronics, medical equipment, industrial automation systems, automotive systems. PLD Programming Languages In the case of programmable logic

Implementation of NOT Gate using NAND Gate ”; Previous Next Before getting into implementing a NOT gate using NAND gate, let’s have a basic overview of NOT gates and NAND gates. What is NOT Gate? NOT gate is a basic logic gate used in digital electronic circuits. The NOT gate has a single input and a single output. The output of the NOT gate is the logical inversion of its input. For this reason, the NOT gate is also known as inverter. The symbol of the standard NOT gate has a triangle pointing to the right with a circle at its right end as shown in figure-1. This circle is referred to as an inversion bubble. The NOT gate produces an output which is the complement or inversion of its input. For example, if we give a HIGH input single, then it provides a LOW output signal. Similarly, when we give a LOW input signal, then it provides a HIGH output signal. Since, the NOT gate is a single input device, therefore, it is not used as a decision making component in the logic circuits. Truth Table of NOT Gate The following is the truth table of NOT gate − Input (A) Output (Y = A’) 0 1 1 0 Boolean Expression of NOT Gate The following is the Boolean expression of the NOT gate − $$\mathrm{Y \: = \: A”}$$ For a NOT gate, if A is 1 (HIGH / TRUE), then Y is 0 (LOW / FALSE), and vice-versa. What is NAND Gate? NAND is a universal logic gate. It is a digital logic gate having two or more input terminals and gives an output depending on the combination of the input signals. NAND represents NOT + AND, i.e. it produces an output which is the inversion or compliment of logic AND operation. Since, NAND is a universal logic gate, therefore, it can be used to implement all kinds of logic operations like OR, AND, NOT. The symbol of the NAND gate is shown in Figure-2. From the symbol, it is clear that it has a shape of standard AND gate with a circle. This circle is known as inversion bubble. The symbol gives the idea about the operation of the NAND gate, i.e. it takes inputs, performs AND operations, and at last takes the inversion of the result of AND operation to provide the final output of the NAND gate. Truth Table of NAND Gate The following is the truth table of the NAND gate − Inputs Output A B Y = (AB)’ 0 0 1 0 1 1 1 0 1 1 1 0 From the truth table of NAND gate, it is clear that the operation of the NAND gate is same as that of the AND gate followed by a NOT gate. For this reason, the symbol of the NAND is like as shown in the Figure-2. Boolean Expression of NAND Gate The following is the Boolean expression of the NAND gate − $$\mathrm{Y \: = \: (AB)”}$$ Now, let us discuss the implementation of NOT gate using NAND gate. Implementation of NOT Gate using NAND Gate As we discussed in the above section that the NAND gate is a universal gate, thus we can use it to realize any basic logic gate. The realization of NOT gate using NAND gate is shown in Figure-3. From Figure-3, it is clear that to realize the NOT gate using the NAND gate, we have to join the two input terminals of the NAND gate to form a single input terminal of the NOT gate, and the output of the NOT gate is taken from the output terminal of the NAND gate. Truth Table of NOT Gate using NAND Gate The following is the truth table of NOT gate using NAND gate − Inputs Output A B Y = (AB)’ = A’ 0 0 1 1 1 0 Hence, this is all about the implementation of NOT gate using NAND gate. Print Page Previous Next Advertisements ”;

BCD to Decimal Converter ”; Previous Next A digital circuit that can convert a binary-coded decimal (BCD) number into an equivalent decimal number is referred to as a BCD-to-decimal converter. The input to a BCD to decimal converter is an 8421 BCD code and the output generated by the converter is a decimal number. The following is the truth table of the BCD to decimal converter describing its operation. BCD Code Decimal B3 B2 B1 B0 0 0 0 0 D0 0 0 0 1 D1 0 0 1 0 D2 0 0 1 1 D3 0 1 0 0 D4 0 1 0 1 D5 0 1 1 0 D6 0 1 1 1 D7 1 0 0 0 D8 1 0 0 1 D9 We can derive the Boolean expressions for each of the decimal outputs in terms of 8421 BCD code. These Boolean expressions are given below − $$\mathrm{D_{0} \: = \: \overline{B_{3}} \: \overline{B_{2}} \: \overline{B_{1}} \: \overline{B_{0}}}$$ $$\mathrm{D_{1} \: = \: \overline{B_{3}} \: \overline{B_{2}} \: \overline{B_{1}} \: B_{0}}$$ $$\mathrm{D_{2} \: = \: \overline{B_{3}} \: \overline{B_{2}} \: B_{1} \: \overline{B_{0}}}$$ $$\mathrm{D_{3} \: = \: \overline{B_{3}} \: \overline{B_{2}} \: B_{1} \: B_{0}}$$ $$\mathrm{D_{4} \: = \: \overline{B_{3}} \: B_{2} \: \overline{B_{1}} \: \overline{B_{0}}}$$ $$\mathrm{D_{5} \: = \: \overline{B_{3}} \: B_{2} \: \overline{B_{1}} \: B_{0}}$$ $$\mathrm{D_{6} \: = \: \overline{B_{3}} \: B_{2} \: B_{1} \: \overline{B_{0}}}$$ $$\mathrm{D_{7} \: = \: \overline{B_{3}} \: B_{2} \: B_{1} \: B_{0}}$$ $$\mathrm{D_{8} \: = \: B_{3} \: \overline{B_{2}} \: \overline{B_{1}} \: \overline{B_{0}}}$$ $$\mathrm{D_{9} \: = \: B_{3} \: \overline{B_{2}} \: \overline{B_{1}} \: B_{0}}$$ The logic circuit implementation of the BCD to decimal converter is shown in the following figure. Print Page Previous Next Advertisements ”;

Application of Shift Registers ”; Previous Next In previous chapter, we discussed four types of shift registers. Based on the requirement, we can use one of those shift registers. Following are the applications of shift registers. Shift register is used as Parallel to serial converter, which converts the parallel data into serial data. It is utilized at the transmitter section after Analog to Digital Converter (ADC) block. Shift register is used as Serial to parallel converter, which converts the serial data into parallel data. It is utilized at the receiver section before Digital to Analog Converter (DAC) block. Shift register along with some additional gate(s) generate the sequence of zeros and ones. Hence, it is used as sequence generator. Shift registers are also used as counters. There are two types of counters based on the type of output from right most D flip-flop is connected to the serial input. Those are Ring counter and Johnson Ring counter. In this chapter, let us discuss about these two counters one by one. Ring Counter In previous chapter, we discussed the operation of Serial In – Parallel Out (SIPO) shift register. It accepts the data from outside in serial form and it requires ‘N’ clock pulses in order to shift ‘N’ bit data. Similarly, ‘N’ bit Ring counter performs the similar operation. But, the only difference is that the output of rightmost D flip-flop is given as input of leftmost D flip-flop instead of applying data from outside. Therefore, Ring counter produces a sequence of states (pattern of zeros and ones) and it repeats for every ‘N’ clock cycles. The block diagram of 3-bit Ring counter is shown in the following figure. The 3-bit Ring counter contains only a 3-bit SIPO shift register. The output of rightmost D flip-flop is connected to serial input of left most D flip-flop. Assume, initial status of the D flip-flops from leftmost to rightmost is $\mathrm{Q_{2}Q_{1}Q_{0} \: = \: 001}$. Here, $\mathrm{Q_{2}}$ & $\mathrm{Q_{0}}$ are MSB & LSB respectively. We can understand the working of Ring counter from the following table. No of positive edge of Clock Serial Input = Q0 Q2(MSB) Q1 Q0(LSB) 0 – 0 0 1 1 1 1 0 0 2 0 0 1 0 3 0 0 0 1 The initial status of the D flip-flops in the absence of clock signal is $\mathrm{Q_{2}Q_{1}Q_{0} \: = \: 001}$. This status repeats for every three positive edge transitions of clock signal. Therefore, the following operations take place for every positive edge of clock signal. Serial input of first D flip-flop gets the previous output of third flip-flop. So, the present output of first D flip-flop is equal to the previous output of third flip-flop. The previous outputs of first and second D flip-flops are right shifted by one bit. That means, the present outputs of second and third D flip-flops are equal to the previous outputs of first and second D flip-flops. Johnson Ring Counter The operation of Johnson Ring counter is similar to that of Ring counter. But, the only difference is that the complemented output of rightmost D flip-flop is given as input of leftmost D flip-flop instead of normal output. Therefore, ‘N’ bit Johnson Ring counter produces a sequence of states (pattern of zeros and ones) and it repeats for every ‘2N’ clock cycles. Johnson Ring counter is also called as Twisted Ring counter and switch tail Ring counter. The block diagram of 3-bit Johnson Ring counter is shown in the following figure. The 3-bit Johnson Ring counter also contains only a 3-bit SIPO shift register. The complemented output of rightmost D flip-flop is connected to serial input of left most D flip-flop. Assume, initially all the D flip-flops are cleared. So, $\mathrm{Q_{2}Q_{1}Q_{0} \: = \: 000}$. Here, $\mathrm{Q_{2}}$ & $\mathrm{Q_{0}}$ are MSB & LSB respectively. We can understand the working of Johnson Ring counter from the following table. No of positive edge of Clock Serial Input = Q0 Q2(MSB) Q1 Q0(LSB) 0 – 0 0 0 1 1 1 0 0 2 1 1 1 0 3 1 1 1 1 4 0 0 1 1 5 0 0 0 1 6 0 0 0 0 The initial status of the D flip-flops in the absence of clock signal is $\mathrm{Q_{2}Q_{1}Q_{0} \: = \: 000}$. This status repeats for every six positive edge transitions of clock signal. Therefore, the following operations take place for every positive edge of clock signal. Serial input of first D flip-flop gets the previous complemented output of third flip-flop. So, the present output of first D flip-flop is equal to the previous complemented output of third flip-flop. The previous outputs of first and second D flip-flops are right shifted by one bit. That means, the present outputs of second and third D flip-flops are equal to the previous outputs of first and second D flip-flops. Print Page Previous Next Advertisements ”;

Binary to Decimal Converter ”; Previous Next A type of code converter used to convert data from binary format to decimal format is called a binary-to-decimal converter. The input to the binary-to-decimal converter is a number represented in a format of 0s and 1s. Then, the converter uses an algorithm to convert the input binary number into an equivalent decimal number. Finally, it generates a decimal code as output. Let us now understand the logic circuit implementation of a binary-to-decimal converter. The truth table of a two-bit binary-to-decimal converter is given below. Binary Input Decimal Output B1 B0 0 0 Q0 0 1 Q1 1 0 Q2 1 1 Q3 Let us now derive the logical expression for each of the decimal outputs. $$\mathrm{Q_{0} \: = \: \overline{B_{1}}\: cdot \:\overline{B_{0}}}$$ $$\mathrm{Q_{1} \: = \: \overline{B_{1}}\: cdot \: B_{0}}$$ $$\mathrm{Q_{2} \: = \: B_{1} \: cdot \:\overline{B_{0}}}$$ $$\mathrm{Q_{3} \: = \: B_{1} \: cdot \: B_{0}}$$ The logic circuit diagram of the binary-to-decimal converter is shown in the following figure. This circuit converts a 2-bit binary number into an equivalent decimal number. However, we can implement the binary-to-decimal converter for any number of bits in the same way. Print Page Previous Next Advertisements ”;

Implementation of OR Gate from NAND Gate ”; Previous Next NAND Gate is a universal logic gate, using which we can realize any logic gate. Read this tutorial to find out how you can realize an OR gate using a NAND gate. Before going into the implementation part, let”s have a brief overview of OR and NAND gates. What is an OR Gate? An OR Gate is a basic logic gate. An OR gate may accept two or more than two inputs, but gives only one output. The OR gate gives a HIGH (Logic 1) output if any one of its inputs is in the HIGH or Logic 1 state, otherwise, it gives a LOW (Logic 0) state as output. Therefore, the output of the OR gate is LOW or Logic 0 state, only if its all inputs are LOW or Logic 0 state. The OR gate is also known as an “any or all gate” or “an inclusive OR gate”. The logic symbol of a two input OR gate is shown in Figure-1. Output Equation of OR Gate If A and B are the input variables and Y is the output variable, then the output equation of the OR gate is given by, $$\mathrm{Y \: = \: A \: + \: B}$$ Where, the ”+” symbol represents the OR operation. It is read as Y is equal to A OR B. Truth Table of OR Gate The table that shows the relationship between inputs and output of a logic gate is referred to as a Truth Table. The following is the truth table for the OR Gate − Input Output A B Y = A + B 0 0 0 0 1 1 1 0 1 1 1 1 What is a NAND Gate? The NAND Gate is a type of universal logic gate. Where, a universal logic gate is one that can be used to realize any kind logical expression or any other type of logic gate. A NAND gate is basically a combination of two basic logic gates namely AND gate and NOT gate, i.e., $$\mathrm{NAND \: Logic \: = \: AND \: Logic \: + \: NOT \: Logic}$$ A NAND gate is the type of logic gate whose output is LOW (Logic 0) when all its inputs are high, and its output is HIGH (Logic 1), when any of its inputs is LOW (Logic 0). Therefore, the operation of the NAND gate is opposite that of the AND gate. The logic symbol of a two input NAND gate is shown in Figure-2. Output Equation of NAND Gate If A and B are the input variables and Y is the output variable of the NAND gate, then its output is given by, $$\mathrm{Y \: = \: \overline{A \: \cdot \: B} \: = \: (A \: \cdot \: B)”}$$ It is read as “Y is equal to A.B whole bar”. Truth Table of NAND Gate The following is the truth table of the NAND gate − Input Output A B Y = (A·B)” 0 0 1 0 1 1 1 0 1 1 1 0 Now, let us discuss the implementation of OR Gate from NAND Gate. Implementation of OR Gate from NAND Gate The NAND gate is a universal gate, therefore, it can be used to realize the OR gate. The implementation of OR gate using the NAND gate is shown in Figure-3. The NAND circuit shown in Figure-3 is equivalent to an OR gate. It is also known as bubbled NAND Gate, where the bubbled NAND gate is equivalent to the OR gate in operation. Theory of OR Gate using NAND Gate To realize the OR gate using NAND gate, we first complement the inputs A and B. This is done by the NAND Gate 1 and 2 in the above Figure-3. Then, these complemented inputs, i.e. A” and B” are applied to a NAND Gate (NAND Gate 3). Thus, we get, $$\mathrm{Y \: = \: \overline{\bar{A} \: \cdot \: \bar{B}}}$$ Using De Morgen”s Law, we have, $$\mathrm{Y \: = \: \bar{\bar{A}} \: + \: \bar{\bar{B}} \: = \: A \: + \: B}$$ This is the output equation of the OR gate. Therefore, the logic circuit of NAND gates in Figure-3 is equivalent to the OR Gate. Print Page Previous Next Advertisements ”;

Binary to Gray Code Converter ”; Previous Next A binary-to-gray code converter is a type of code converter that can translate a binary code into its equivalent gray code. The binary-to-gray code converter accepts a binary number as input and produces a corresponding gray code as output. Here is the truth table explaining the operation of a 4-bit binary-to-gray code converter. Binary Code Gray Code B3 B2 B1 B0 G3 G2 G1 G0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0 Let us derive the Boolean expressions for the gray code output bits. For this, we will simplify the truth table using the K-map technique. K-Map for Gray Code Bit G0 The K-Map simplification to obtain the Boolean expression for the gray code bit G0 is shown in the following figure. Hence, the Boolean expression for the gray code bit G0 is, $$\mathrm{G_{0} \: = \: \overline{B_{1}} \: B_{0} \: + \ B_{1} \: \overline{B_{0}} \: = \: B_{0} \: \oplus \: B_{1}}$$ K-Map for Gray Code Bit G1 The K-Map simplification for the gray code bit G1 is shown below − Thus, the Boolean expression for the gray code bit G1 is, $$\mathrm{G_{1} \: = \: \overline{B_{2}} \: B_{1} \: + \ B_{2} \: \overline{B_{1}} \: = \: B_{1} \: \oplus \: B_{2}}$$ K-Map for Gray Code Bit G2 The K-Map simplification for the gray code bit G2 is depicted in the following figure − The Boolean expression for the gray code bit G2 will be, $$\mathrm{G_{2} \: = \: \overline{B_{3}} \: B_{2} \: + \ B_{3} \: \overline{B_{2}} \: = \: B_{2} \: \oplus \: B_{3}}$$ K-Map for Gray Code Bit G3 The K-Map simplification for the gray code bit G3 is shown in the following figure − Hence, the Boolean expression for the gray code bit G3 is, $$\mathrm{G_{3} \: = \: B_{3}}$$ Let us now utilize these Boolean expressions to implement the logic circuit of the binary-to-gray code converter. The following figure shows the logic circuit diagram of a 4-bit binary code to gray code converter − This circuit can convert a 4-bit binary number into an equivalent gray code. We can follow the same procedure to design a binary-to-gray code converter for any number of bits. Print Page Previous Next Advertisements ”;

Digital to Analog Converter ”; Previous Next A Digital to Analog Converter (DAC) converts a digital input signal into an analog output signal. The digital signal is represented with a binary code, which is a combination of bits 0 and 1 while the analog signal is a continuous time function. This chapter deals with Digital to Analog Converters in detail. The block diagram of DAC is shown in the following figure − A Digital to Analog Converter (DAC) consists of a number of binary inputs and a single output. In general, the number of binary inputs of a DAC will be a power of two. Types of Digital to Analog Converters Depending on the construction and structure, there are two types of digital to analog converters, they are − Weighted Resistor DAC R-2R Ladder DAC The following sections discuss about these two types of DACs in detail. Weighted Resistor DAC A weighted resistor DAC produces an analog output, which is almost equal to the digital (binary) input by using binary weighted resistors in the inverting adder circuit. In short, a binary weighted resistor DAC is called as weighted resistor DAC. The circuit diagram of a 3-bit binary weighted resistor DAC is shown in the following figure − Recall that the bits of a binary number can have only one of the two values. i.e., either 0 or 1. Let the 3-bit binary input is b2b1b0. Here, the bits b2 and b0 denote the Most Significant Bit (MSB) and Least Significant Bit (LSB) respectively. The digital switches shown in the above figure will be connected to ground, when the corresponding input bits are equal to ”0”. Similarly, the digital switches shown in the above figure will be connected to the negative reference voltage, −VR when the corresponding input bits are equal to ”1”. In the above circuit, the non-inverting input terminal of an op-amp is connected to ground. That means zero volts is applied at the non-inverting input terminal of op-amp. According to the virtual short concept, the voltage at the inverting input terminal of op-amp is same as that of the voltage present at its non-inverting input terminal. So, the voltage at the inverting input terminal’s node will be zero volts. The nodal equation at the inverting input terminal’s node is − $$\mathrm{\frac{0 \: + \: V_{R}b_{2}}{2^{0}R} \: + \: \frac{0 \: + \: V_{R}b_{1}}{2^{1}R} \: + \: \frac{0 \: + \: V_{R}b_{0}}{2^{2}R} \: + \: \frac{0 \: – \: V_{0}}{R_{f}} \: = \: 0}$$ $$\mathrm{\Rightarrow \: \frac{V_{0}}{R_{f}} \: = \: \frac{V_{R}b_{2}}{2^{0}R} \: + \: \frac{V_{R}b_{1}}{2^{1}R} \: + \: \frac{V_{R}b_{0}}{2^{2}R}}$$ $$\mathrm{\Rightarrow \: V_{0} \: = \: \frac{V_{R}R_{f}}{R}(\frac{b_{2}}{2^{0}} \: + \: \frac{b_{1}}{2^{1}} \: + \: \frac{b_{0}}{2^{2}})}$$ Substituting, R = 2Rf in the above equation, $$\mathrm{V_{0} \: = \: \frac{V_{R}R_{f}}{2R_{f}}(\frac{b_{2}}{2^{0}} \: + \: \frac{b_{1}}{2^{1}} \: + \: \frac{b_{0}}{2^{2}})}$$ $$\mathrm{\therefore \: V_{0} \: = \: \frac{V_{R}}{2}(\frac{b_{2}}{2^{0}} \: + \: \frac{b_{1}}{2^{1}} \: + \: \frac{b_{0}}{2^{2}})}$$ The above equation represents the output voltage equation of a 3-bit binary weighted resistor DAC. Since the number of bits are three in the binary (digital) input, we will get seven possible values of output voltage by varying the binary input from 000 to 111 for a fixed reference voltage, VR. We can write the generalized output voltage equation of an N-bit binary weighted resistor DAC as shown below based on the output voltage equation of a 3-bit binary weighted resistor DAC. $$\mathrm{\therefore \: V_{0} \: = \: \frac{V_{R}}{2}(\frac{b_{N-1}}{2^{0}} \: + \: \frac{b_{N-2}}{2^{1}} \: + \dotso \: + \: \frac{b_{0}}{2^{N-1}})}$$ Disadvantages of Weighted Resistor DAC The disadvantages of the binary weighted resistor DAC are as follows − The difference between the resistance values corresponding to LSB & MSB will increase as the number of bits present in the digital input increases. It is difficult to design more accurate resistors as the number of bits present in the digital input increases. R-2R Ladder DAC The R-2R Ladder DAC overcomes the disadvantages of a binary weighted resistor DAC. As the name suggests, R-2R Ladder DAC produces an analog output, which is almost equal to the digital (binary) input by using a R-2R ladder network in the inverting adder circuit. The circuit diagram of a 3-bit R-2R Ladder DAC is shown in the following figure − Recall that the bits of a binary number can have only one of the two values. i.e., either 0 or 1. Let the 3-bit binary input is b2b1b0. Here, the bits b2 and b0 denote the Most Significant Bit (MSB) and Least Significant Bit (LSB) respectively. The digital switches shown in the above figure will be connected to ground, when the corresponding input bits are equal to ”0”. Similarly, the digital switches shown in above figure will be connected to the negative reference voltage, −VR when the corresponding input bits are equal to ”1”. It is difficult to get the generalized output voltage equation of a R-2R Ladder DAC. But we can find the analog output voltage values of R-2R Ladder DAC for individual binary input combinations easily. Advantages of R-2R Ladder DAC The advantages of a R-2R Ladder DAC are as follows − R-2R Ladder DAC contains only two values of resistor: R and 2R. So, it is easy to select and design more accurate resistors. If a greater number of bits are present in the digital input, then we have to include required number of R-2R sections additionally. Due to the above advantages, R-2R Ladder DAC is preferable over binary weighted resistor DAC. Important Parameters of DACs The following are some key parameters and factors that we must consider while selecting a digital to analog converter for a specific application − Resolution The number of

BCD to Excess-3 Converter ”; Previous Next A type of code converter in digital electronics that is used to convert a binary-coded decimal number into an equivalent excess-3 code is called a BCD to excess-3 converter. Hence, in the case of a BCD to excess-3 code converter, the input is an 8421 BCD code and the output is an XS-3 code. The following is the truth table of a BCD to excess-3 code converter − BCD Code Excess-3 Code B3 B2 B1 B0 X3 X2 X1 X0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 1 0 1 0 X X X X 1 0 1 1 X X X X 1 1 0 0 X X X X 1 1 0 1 X X X X 1 1 1 0 X X X X 1 1 1 1 X X X X Let us solve the truth table using the K-map to derive the Boolean expressions for the XS-3 output bits X0, X1, X2, and X3. K-Map for XS-3 Bit X0 The K-map simplification for the XS-3 bit X0 is shown in the following figure − On simplifying this K-map, we obtain the following Boolean expression, $$\mathrm{X_{0} \: = \: \overline{B_{0}}}$$ K-Map for XS-3 Bit X1 The K-map simplification for the XS-3 bit X1 is depicted below − This K-map simplification gives the following Boolean expression, $$\mathrm{X_{1} \: = \: \overline{B_{1}} \: \overline{B_{0}} \: + \: B_{1} \: B_{0}}$$ K-Map for XS-3 Bit X2 The K-map simplification for the XS-3 bit X2 is shown in the figure below. On simplifying this K-map, we obtain the following Boolean expression, $$\mathrm{X_{2} \: = \: B_{2} \: B_{1} \: + \: \overline{B_{2}} \: B_{0} \: + \: B_{2} \: \overline{B_{1}} \: \overline{B_{0}}}$$ K-Map for XS-3 Bit X3 The K-map simplification for the XS-3 bit X3 is depicted in the figure below − This K-map gives the following Boolean expression, $$\mathrm{X_{3} \: = \: B_{3} \: + \: B_{2} \: B_{1} \: + \: B_{2} \: B_{0}}$$ The logic circuit diagram of the BCD to XS-3 converter is shown in the following figure − This circuit converters a 4-bit BCD code into an equivalent XS-3 code. Print Page Previous Next Advertisements ”;

Implementation of NOR Gate from NAND Gate ”; Previous Next NOR and NAND gates are universal logic gates, using which we can implement any logic gate or any other logical expression. Read this tutorial to find out how you can implement a NOR gate using a NAND gate. What is a NOR Gate? NOR Gate is a type of universal logic gate, because this logic gate can be used for implementation of any other type of logic gate. NOR means “NOT + OR”. That means the OR output is NOTed or inverted. Therefore, the NOR gate is a combination of OR gate and a NOT gate. $$\mathrm{NOR \: Gate \: = \: OR \: Gate \:+ \: NOT \: Gate}$$ A NOR gate is a type of logic gate whose output is HIGH (Logic 1), only when all its inputs are LOW (Logic 0), and it gives an output LOW (Logic 0), even if any of its inputs become HIGH (Logic 1). The logic symbol of a two input NOR gate is shown in Figure-1. Output Equation of NOR Gate If A and B are the input variables and Y is the output variable of the NOR gate, then the output of the NOR gate is given by, $$\mathrm{Y \: = \: \overline{A \: + \: B} \: = \: (A \: + \: B)”}$$ It is read as “Y is equal to A plus B whole bar”. Truth Table of NOR Gate The table that shows the relationship between inputs and output of a logic gate is referred to as a truth table. The following is the truth table of the NOR gate − Input Output A B Y = (A + B)” 0 0 1 0 1 0 1 0 0 1 1 0 What is a NAND Gate? The NAND Gate is a type of universal logic gate. Where, a universal logic gate is one that can be used to realize any kind logical expression or any other type of logic gate. A NAND gate is basically a combination of two basic logic gates namely AND gate and NOT gate, i.e., $$\mathrm{NAND \: Logic \: = \: AND \: Logic \: = \: NOT \: Logic}$$ A NAND gate is the type of logic gate whose output is LOW (Logic 0) when all its inputs are high, and its output is HIGH (Logic 1), when any of its inputs is LOW (Logic 0). Therefore, the operation of the NAND gate is opposite that of the AND gate. The logic symbol of a two input NAND gate is shown in Figure-2. Output Equation of NAND Gate If A and B are the input variables and Y is the output variable of the NAND gate, then its output is given by, $$\mathrm{Y \: = \: \overline{A \: \cdot \: B} \: = \: (A \: + \: B)”}$$ It is read as “Y is equal to A.B whole bar”. Truth Table of NAND Gate The following is the truth table of the NAND gate − Input Output A B Y = (A·B)” 0 0 1 0 1 1 1 0 1 1 1 0 Now, let us discuss the implementation of NOR Gate from NAND Gate. Implementation of NOR Gate from NAND Gate As mentioned above, the NAND gate is a universal logic gate, therefore, it can be used to realize the any other logic gate. The implementation of NOR gate using the NAND gate is shown in Figure-3. From the logic circuit, it is clear that for the implementation of NOR gate using NAND gates only, we require 4 NAND gates. The first two NAND gates perform the complement of input variables A and B, the third NAND gate produce the NAND output of the complemented inputs, i.e. A” and B”. Finally, the fourth NAND gate again operates as an inverter and produce the output Y. This output Y is the equivalent to the output of the NOR gate. Output Equation The output of the first and second NAND gates is, $$\mathrm{Y_{1} \: = \: \bar{A} \:\: and \:\: Y_{2} \: = \: \bar{B}}$$ The output of the third NAND gates is, $$\mathrm{Y_{3} \: = \: \overline{\bar{A} \: \cdot \: \bar{B}} \: = \: A \: + \: B}$$ The output of the fourth NAND gate is, $$\mathrm{Y \: = \: \overline{A \: + \: B}}$$ Hence, this is the output of a NOR Gate. In this way, we can implement a NOR gate using NAND gates only. Print Page Previous Next Advertisements ”;