Category: digital-electronics

Programmable Logic Devices ”; Previous Next Programmable Logic Devices (PLDs) are a collection of integrated circuits which are configured to perform various logical functions. PLDs play an important role in the field of engineering and technology, as they form the basis of innovation and support engineers to develop automated digital systems to improve process flexibility and efficiency. Here, “programmable” means defining a function that can be performed multiple times without human intervention. Programmable Logic Devices (PLDs) are the integrated circuits. They contain an array of AND gates & another array of OR gates. There are three kinds of PLDs based on the type of array(s), which has programmable feature. Programmable Read Only Memory Programmable Array Logic Programmable Logic Array The process of entering the information into these devices is known as programming. Basically, users can program these devices or ICs electrically in order to implement the Boolean functions based on the requirement. Here, the term programming refers to hardware programming but not software programming. In this chapter, we will explain the basic concepts of programmable logic devices, their types, advantages, limitations, and applications. Programmable Read Only Memory (PROM) Read Only Memory (ROM) is a memory device, which stores the binary information permanently. That means, we can’t change that stored information by any means later. If the ROM has programmable feature, then it is called as Programmable ROM (PROM). The user has the flexibility to program the binary information electrically once by using PROM programmer. PROM is a programmable logic device that has fixed AND array & Programmable OR array. The block diagram of PROM is shown in the following figure. Here, the inputs of AND gates are not of programmable type. So, we have to generate 2n product terms by using 2n AND gates having n inputs each. We can implement these product terms by using nx2n decoder. So, this decoder generates ‘n’ min terms. Here, the inputs of OR gates are programmable. That means, we can program any number of required product terms, since all the outputs of AND gates are applied as inputs to each OR gate. Therefore, the outputs of PROM will be in the form of sum of min terms. Example Let us implement the following Boolean functions using PROM. $$\mathrm{A(X,Y,Z):=:sum mleft ( 5,6,7 right )}$$ $$\mathrm{B(X,Y,Z):=:sum mleft ( 3,5,6,7 right )}$$ The given two functions are in sum of min terms form and each function is having three variables X, Y & Z. So, we require a 3 to 8 decoder and two programmable OR gates for producing these two functions. The corresponding PROM is shown in the following figure. Here, 3 to 8 decoder generates eight min terms. The two programmable OR gates have the access of all these min terms. But, only the required min terms are programmed in order to produce the respective Boolean functions by each OR gate. The symbol ‘X’ is used for programmable connections. What is a Programmable Logic Device? A Programmable Logic Device (PLD) can be defined as an integrated circuit (IC) which can be programmed to perform specific functions. Here, programming means we can define a set of instructions that can be executed to perform the functions multiple times without need of any human intervention. The primary need of developing PLDs is occurred to implement digital logic functions that can copy the behavior of conventional logic circuits and replicate it many times. However, the PLDs are different from normal digital logic circuits in terms of programmability, which means we can define the desired logic functions by setting a collection of instructions in the device. Types of PLDs Based on the type of device used, Programmable Logic Devices (PLDs) can be classified into the following two types − Bipolar PLDs CMOS PLDs Let us discuss each type of programmable logic device in detail. Bipolar PLDs Bipolar PLDs are the types of programmable logic devices in which Bipolar Junction Transistor (BJT) is the main functional device. Bipolar PLDs are the older versions of programmable logic devices. Thus, they were commonly used before the development of CMOS PLDs. The following are some important characteristics of the bipolar programmable logic devices − Bipolar PLDs provide fast switching speeds and hence they can operate at higher frequencies. Bipolar PLDs are better suited for applications involving rapid signal processing and require fast response times. Bipolar PLDs require more power to operate. Bipolar PLDs have better immunity to electronic noise and interference. All these characteristics make the bipolar programmable logic devices well-suited to use in the applications where high-speed operation and reliability are critical, such as aerospace, military, and telecommunications systems. CMOS PLDs CMOS PLDs stand for Complementary Metal Oxide Semiconductor Programmable Logic Devices. As their name implies, CMOS PLDs use the CMOS transistors i.e., NMOS (N-channel Metal Oxide Semiconductor) and PMOS (P-channel Metal Oxide Semiconductor) transistors as the fundamental component. CMOS PLDs are basically the modern versions of PLDs and are widely used in modern digital systems due to their numerous advantages. Some important characteristics of CMOS PLDs are described below − CMOS PLDs require very less amount of power to operate. Hence, this characteristic makes the CMOS PLDs well-suited to use in battery-power devices where energy efficiency is an important factor. CMOS PLDs are more reliable and robust. As they are designed to withstand against various environmental factors like high/low temperatures, voltage fluctuations, and different radiation interferences. CMOS PLDs are also excellent in terms of scalability. CMOS PLDs are newer PLD devices and hence are very commonly used in various modern electronics devices like consumer electronics, medical equipment, industrial automation systems, automotive systems. PLD Programming Languages In the case of programmable logic

Implementation of NOT Gate using NAND Gate ”; Previous Next Before getting into implementing a NOT gate using NAND gate, let’s have a basic overview of NOT gates and NAND gates. What is NOT Gate? NOT gate is a basic logic gate used in digital electronic circuits. The NOT gate has a single input and a single output. The output of the NOT gate is the logical inversion of its input. For this reason, the NOT gate is also known as inverter. The symbol of the standard NOT gate has a triangle pointing to the right with a circle at its right end as shown in figure-1. This circle is referred to as an inversion bubble. The NOT gate produces an output which is the complement or inversion of its input. For example, if we give a HIGH input single, then it provides a LOW output signal. Similarly, when we give a LOW input signal, then it provides a HIGH output signal. Since, the NOT gate is a single input device, therefore, it is not used as a decision making component in the logic circuits. Truth Table of NOT Gate The following is the truth table of NOT gate − Input (A) Output (Y = A’) 0 1 1 0 Boolean Expression of NOT Gate The following is the Boolean expression of the NOT gate − $$\mathrm{Y \: = \: A”}$$ For a NOT gate, if A is 1 (HIGH / TRUE), then Y is 0 (LOW / FALSE), and vice-versa. What is NAND Gate? NAND is a universal logic gate. It is a digital logic gate having two or more input terminals and gives an output depending on the combination of the input signals. NAND represents NOT + AND, i.e. it produces an output which is the inversion or compliment of logic AND operation. Since, NAND is a universal logic gate, therefore, it can be used to implement all kinds of logic operations like OR, AND, NOT. The symbol of the NAND gate is shown in Figure-2. From the symbol, it is clear that it has a shape of standard AND gate with a circle. This circle is known as inversion bubble. The symbol gives the idea about the operation of the NAND gate, i.e. it takes inputs, performs AND operations, and at last takes the inversion of the result of AND operation to provide the final output of the NAND gate. Truth Table of NAND Gate The following is the truth table of the NAND gate − Inputs Output A B Y = (AB)’ 0 0 1 0 1 1 1 0 1 1 1 0 From the truth table of NAND gate, it is clear that the operation of the NAND gate is same as that of the AND gate followed by a NOT gate. For this reason, the symbol of the NAND is like as shown in the Figure-2. Boolean Expression of NAND Gate The following is the Boolean expression of the NAND gate − $$\mathrm{Y \: = \: (AB)”}$$ Now, let us discuss the implementation of NOT gate using NAND gate. Implementation of NOT Gate using NAND Gate As we discussed in the above section that the NAND gate is a universal gate, thus we can use it to realize any basic logic gate. The realization of NOT gate using NAND gate is shown in Figure-3. From Figure-3, it is clear that to realize the NOT gate using the NAND gate, we have to join the two input terminals of the NAND gate to form a single input terminal of the NOT gate, and the output of the NOT gate is taken from the output terminal of the NAND gate. Truth Table of NOT Gate using NAND Gate The following is the truth table of NOT gate using NAND gate − Inputs Output A B Y = (AB)’ = A’ 0 0 1 1 1 0 Hence, this is all about the implementation of NOT gate using NAND gate. Print Page Previous Next Advertisements ”;

Design Full Adder Using Half Adder ”; Previous Next In data processing, addition of operands is one of the most basic operations performed by different electronic devices like computers, calculators, etc. The electronic circuit that is designed to perform the addition of two or more numbers, more specifically binary numbers, is known as adder. As we know, the logic circuits use binary number system to perform the operations, hence the adder is also referred to as a binary adder. Types of Adders Depending on the number of binary digits that the adder circuit can add, adders (or binary adders) are of two types − Half Adder Full Adder Here, we will discuss the implementation of full adder using half adder. But before that let’s have a look into the basics of half adder and full adder. What is a Half Adder? Half adder is a combinational logic circuit that is designed to add two binary digits. The half adder provides the output along with a carry (if any). The half adder circuit can be designed by connecting an XOR gate and one AND gate. It has two input terminals and two output terminals for sum (S) and carry (C). The block diagram and circuit diagram of a half adder are shown in Figure-1. In the half adder, the output of the XOR gate is the sum of two bits and the output of the AND gate is the carry bit. However, in the half-adder circuit, the carry obtained in one addition will not be forwarded in the next addition. The output equation of the half adder are, $$\mathrm{Sum, \: S \: = \: A \: \oplus \: B}$$ $$\mathrm{Carry, \: C \: = \: A \: \cdot \ B}$$ What is a Full Adder? Full adder is also a combinational logic circuit that can add two binary digits (bits) and a carry bit, and produces a sum bit and a carry bit as output. In other words, a combinational circuit which is designed to add three binary digits and produces two outputs (sum and carry) is known as a full adder. Thus, a full adder circuit adds three binary digits, where two are the inputs and one is the carry forwarded from the previous addition. The block diagram and circuit diagram of the full adder are shown in Figure-2. It is clear that the logic circuit of a full adder consists of one XOR gate, three AND gates and one OR gate, which are connected together as shown in Figure-2. Here, A and B are the input bits, Cin is the carry from previous addition, S is the sum bit, and Cout is the output carry bit. The output equations of the full adder are, $$\mathrm{Sum, \: S \: = \: A \: \oplus \: B \: \oplus \: C_{in}}$$ $$\mathrm{Carry, \: C_{out} \: = \: Ab \: + \: AC_{in} \: + \: BC_{in}}$$ Now, let us discuss the realization of the full adder using half adders Implementation of Full Adder using Half Adder The logic diagram of the full adder using two half adders is shown in Figure-3 − The block diagram of a full adder using two half adders is shown in Figure-4. From the logic diagram of the full adder using half adders, it is clear that we require two XOR gates, two AND gates and one OR gate for the implementation of a full adder circuit using half-adders. However, the implementation of full adder using half adder has a major disadvantage that is the increased propagation delay. That means, the input bits must propagate through several gates in succession that increases the total propagation delay of the full adder circuit. Print Page Previous Next Advertisements ”;

DAC and ADC ICs ”; Previous Next A digital to analog converter is an electronic device that converters a digital signal into analog format. On the other hand, an analog to digital converter is an electronic device that converters an analog signal into digital format. Both DAC (Digital to Analog Converter) and ADC (Analog to Digital Converter) play an important role in different fields of electronic such as communication, signal processing, computing technologies, control and automation systems, and more. With the advancement of technology, we can design and implement the analog to digital converters and digital to analog converters in the form of IC or integrated circuits. This chapter is meant for explaining some important ADC and DAC ICs commonly used in electronic circuits and systems. What are DAC and ADC ICs? DAC and ADC ICs are small electronic devices and integrated circuits used in the field of electronics to convert a digital signal into analog format and analog signal into digital format respectively. The ADC IC (Analog to Digital Converter IC) is used to convert analog signals into digital format. These ICs take the analog signals as input and sample them at regular intervals of time. Then, they produce digital representation of the analog input signal as output. There is another type of IC called DAC IC (Digital to Analog Converter IC) that is used to convert digital signals into analog format. Hence, the DAC ICs take digital signals as input and produce their analog representation as output. The ADC and DAC ICs are important components in several different types of electronic systems where converting signals between the analog and digital formats are crucial. Popular DAC and ADC ICs The following are some commonly used DAC and ADC ICs that are widely used in various electronic applications − ADC 0809 (8-Bit ADC IC) ICL 7109 (12-Bit Binary ADC IC) DAC 0808 (8-Bit DAC IC) Let us discuss about these ADC and DAC ICs in detail along with their features and applications. ADC 0809 IC The ADC 0809 IC is an analog to digital converter IC. It is a monolithic CMOS device that consists of an 8-bit analog to digital converter, an 8-bit multiplexer, and a microprocess compatible control unit. The ADC 0809 IC uses successive approximation technique to perform analog to digital conversion. It comes in a 28-pin molded IC carrier package. The pin diagram of the ADC 0809 IC is shown in the following figure. This IC is one of the widely used ADC ICs in various digital electronics and microcontroller-based circuits and systems to convert analog signals into their digital format. Features of ADC 0809 IC Some of the key features of ADC 0809 IC are listed below − The ADC 0809 IC is an 8-bit analog to digital converter IC. Hence, it can represent an analog input signal with a resolution of 8 bits or 28 = 256 possible discrete values in digital format. The ADC 0809 IC provides an easy interfacing with all microprocessors. It does not require the external zero or full-scale adjustments. It also consists an 8-channel single ended analog signal multiplexer. It can operate ratiometrically or with a 5 V DC voltage or an analog span adjusted voltage reference. The output of the ADC 0809 IC meets the TTL voltage level requirements. The ADC 0809 IC can operate with low power consumption, typically 15 mW that makes making it best suited for batterypowered devices. It can support 0 V to 5V input analog voltage range with a single supply of 5 V DC. It has a conversion time of around 100 µs. Applications of ADC 0809 IC The ADC 0809 IC is an ideal device in various applications such as automation, process and machine control, consumer electronics, automotives, etc. Some common applications of this ADC IC are listed here − The ADC 0809 IC is most commonly used in data acquisition systems to convert analog input signals received from sensors, transducers, and other analog measuring devices into digital format to process and analyze them using digital systems. The ADC 0809 IC is also used in different applications in the field of instrumentation and control engineering. It is mainly employed for precise measurement and monitoring of analog signals like temperature, pressure, and motor control. In the field of industrial automation, the ADC 0809 IC is used for digitalization of analog process and control signals which are then used for automation and monitoring of control and manufacturing processes. The ADC 0809 IC is also used in various consumer electronic devices such as digital multimeters, audio and music systems, etc. for providing an interface between analog signals and digital circuits. ICL 7109 IC The ICL 7109 IC is a monolithic 12-Bit analog to digital converter (ADC) IC primarily designed for easy interfacing with microprocessor-based systems and Universal Asynchronous Receiver-Transmitter (UART). The ICL 7109 IC comes in a 40-pin IC package whose pin configuration diagram is shown in the following figure − Features of ICL 7109 IC Some of the key features of the ICL 7109 ADC IC are described below − The ICL 7109 IC is a 12-bit dual slope integrating analog to digital converter IC. Hence, it provides a resolution of 12-bits that enables it to represent the analog input signals with a higher precision in digital format. The ICL 7109 IC provides an easy interfacing with microprocessors. This feature makes it ideally suitable for applications where analog signals are required to be processed or analyzed using digital systems like computers. The ICL 7109 IC also provides facility of interfacing with UART (Universal Asynchronous Receiver/Transmitter) systems. This feature allows for serial data transmission and communication with external

Digital Electronics – Demultiplexers ”; Previous Next What is a Demultiplexer? A Demultiplexer is a combinational logic circuit that accepts a single input and distributes it over several output lines. Demultiplexer is also termed as DEMUX in short. As Demultiplexer is used to transmit the same data to different destinations, hence it is also known as data distributor. There is another combinational logic circuit named multiplexer which performs opposite operation of the Demultiplexer, i.e. accepts several inputs and transmits one of them at time to the output line. From the definition, we can state that a Demultiplexer is a 1-to-2n device. The functional block diagram of a typical 1×2n Demultiplexer is shown in Figure-1. It can be seen that the Demultiplexer has only one data input line, 2n output lines, and n select lines. The logic level applied to select lines of the Demultiplexer determines the output channel to which the input data will be transmitted. Demultiplexer circuit are the combinational logic circuit widely used in digital decoders and Boolean function generator circuits. Types of Demultiplexer Based on the number of output lines (2n), Demultiplexers can be classified into several types. Some commonly used types of Demultiplexers are − 1×2 Demultiplexer 1×4 Demultiplexer Now, let us briefly discuss each type of Demultiplexer. 1×2 Demultiplexer The functional block diagram of a 1×2 Demultiplexer is shown in Figure-2. The 1×2 Demultiplexer consists of 1 input line (I), 1 select line (S), and 2 output lines (Y0 and Y1). The logic level applied at the select line determines the output line to which the input data will be transmitted. The operation of the 1×2 Demultiplexer can be analyzed with the help of its function table given below. Select Line Outputs S Y1 Y0 0 0 I 1 I 0 From this function table of 1×2 Demultiplexer, we can directly derive the Boolean expression for each output as follow. $$\mathrm{Y_{0} \: = \: \bar{S} \: I}$$ And, $$\mathrm{Y_{1} \: = \: S \: I}$$ 1×4 Demultiplexer The functional block diagram of 1×4 Demultiplexer is shown in Figure-3. The 1×4 Demultiplexer has 1 input line (I), 2 select line (S0 and S1), and 4 output lines (Y0, Y1, Y2, and Y3). The logic level applied to the select lines determines the output line to which the input data (I) will be transmitted. The operation of the 1×4 Demultiplexer can be understood with the help of its function table given below. Select Line Outputs S1 S0 Y3 Y2 Y1 Y0 0 0 0 0 0 I 0 1 0 0 I 0 1 0 0 I 0 0 1 1 I 0 0 0 From this truth table of 1×4 Demultiplexer, we can directly write the Boolean expression for each output as follow. $$\mathrm{Y_{0} \: = \: bar{S_{1}} \: bar{S_{0}} \: I}$$ $$\mathrm{Y_{1} \: = \: bar{S_{1}} \: S_{0} \: I}$$ $$\mathrm{Y_{2} \: = \: S_{1} \: bar{S_{0}} \: I}$$ $$\mathrm{Y_{3} \: = \: S_{1} \: S_{0} \: I}$$ We can easily understand the operation of the above circuit. Similarly, you can implement 1×8 Demultiplexer and 1×16 Demultiplexer by following the same procedure. Implementation of Higher-order Demultiplexer Now, let us implement the following two higher-order Demultiplexers using lower-order Demultiplexers. 1×8 Demultiplexer 1×16 Demultiplexer 1×8 Deultiplexer In this section, let us implement 1×8 Demultiplexer using 1×4 Demultiplexers and 1×2 Demultiplexer. We know that 1×4 Demultiplexer has single input, two selection lines and four outputs. Whereas, 1×8 Demultiplexer has single input, three selection lines and eight outputs. So, we require two 1×4 Demultiplexers in second stage in order to get the final eight outputs. Since, the number of inputs in second stage is two, we require 1×2 Demultiplexer in first stage so that the outputs of first stage will be the inputs of second stage. Input of this 1×2 Demultiplexer will be the overall input of 1×8 Demultiplexer. Let the 1×8 Demultiplexer has one input I, three selection lines s2, s1 & s0 and outputs Y7 to Y0. The Truth table of 1×8 Demultiplexer is shown below. Selection Inputs Outputs s2 s1 s0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0 0 0 0 0 0 0 0 0 0 I 0 0 1 0 0 0 0 0 0 I 0 0 1 0 0 0 0 0 0 I 0 0 0 1 1 0 0 0 0 I 0 0 0 1 0 0 0 0 0 I 0 0 0 0 1 0 1 0 0 I 0 0 0 0 0 1 1 0 0 I 0 0 0 0 0 0 1 1 1 I

BCD to Decimal Converter ”; Previous Next A digital circuit that can convert a binary-coded decimal (BCD) number into an equivalent decimal number is referred to as a BCD-to-decimal converter. The input to a BCD to decimal converter is an 8421 BCD code and the output generated by the converter is a decimal number. The following is the truth table of the BCD to decimal converter describing its operation. BCD Code Decimal B3 B2 B1 B0 0 0 0 0 D0 0 0 0 1 D1 0 0 1 0 D2 0 0 1 1 D3 0 1 0 0 D4 0 1 0 1 D5 0 1 1 0 D6 0 1 1 1 D7 1 0 0 0 D8 1 0 0 1 D9 We can derive the Boolean expressions for each of the decimal outputs in terms of 8421 BCD code. These Boolean expressions are given below − $$\mathrm{D_{0} \: = \: \overline{B_{3}} \: \overline{B_{2}} \: \overline{B_{1}} \: \overline{B_{0}}}$$ $$\mathrm{D_{1} \: = \: \overline{B_{3}} \: \overline{B_{2}} \: \overline{B_{1}} \: B_{0}}$$ $$\mathrm{D_{2} \: = \: \overline{B_{3}} \: \overline{B_{2}} \: B_{1} \: \overline{B_{0}}}$$ $$\mathrm{D_{3} \: = \: \overline{B_{3}} \: \overline{B_{2}} \: B_{1} \: B_{0}}$$ $$\mathrm{D_{4} \: = \: \overline{B_{3}} \: B_{2} \: \overline{B_{1}} \: \overline{B_{0}}}$$ $$\mathrm{D_{5} \: = \: \overline{B_{3}} \: B_{2} \: \overline{B_{1}} \: B_{0}}$$ $$\mathrm{D_{6} \: = \: \overline{B_{3}} \: B_{2} \: B_{1} \: \overline{B_{0}}}$$ $$\mathrm{D_{7} \: = \: \overline{B_{3}} \: B_{2} \: B_{1} \: B_{0}}$$ $$\mathrm{D_{8} \: = \: B_{3} \: \overline{B_{2}} \: \overline{B_{1}} \: \overline{B_{0}}}$$ $$\mathrm{D_{9} \: = \: B_{3} \: \overline{B_{2}} \: \overline{B_{1}} \: B_{0}}$$ The logic circuit implementation of the BCD to decimal converter is shown in the following figure. Print Page Previous Next Advertisements ”;

Application of Shift Registers ”; Previous Next In previous chapter, we discussed four types of shift registers. Based on the requirement, we can use one of those shift registers. Following are the applications of shift registers. Shift register is used as Parallel to serial converter, which converts the parallel data into serial data. It is utilized at the transmitter section after Analog to Digital Converter (ADC) block. Shift register is used as Serial to parallel converter, which converts the serial data into parallel data. It is utilized at the receiver section before Digital to Analog Converter (DAC) block. Shift register along with some additional gate(s) generate the sequence of zeros and ones. Hence, it is used as sequence generator. Shift registers are also used as counters. There are two types of counters based on the type of output from right most D flip-flop is connected to the serial input. Those are Ring counter and Johnson Ring counter. In this chapter, let us discuss about these two counters one by one. Ring Counter In previous chapter, we discussed the operation of Serial In – Parallel Out (SIPO) shift register. It accepts the data from outside in serial form and it requires ‘N’ clock pulses in order to shift ‘N’ bit data. Similarly, ‘N’ bit Ring counter performs the similar operation. But, the only difference is that the output of rightmost D flip-flop is given as input of leftmost D flip-flop instead of applying data from outside. Therefore, Ring counter produces a sequence of states (pattern of zeros and ones) and it repeats for every ‘N’ clock cycles. The block diagram of 3-bit Ring counter is shown in the following figure. The 3-bit Ring counter contains only a 3-bit SIPO shift register. The output of rightmost D flip-flop is connected to serial input of left most D flip-flop. Assume, initial status of the D flip-flops from leftmost to rightmost is $\mathrm{Q_{2}Q_{1}Q_{0} \: = \: 001}$. Here, $\mathrm{Q_{2}}$ & $\mathrm{Q_{0}}$ are MSB & LSB respectively. We can understand the working of Ring counter from the following table. No of positive edge of Clock Serial Input = Q0 Q2(MSB) Q1 Q0(LSB) 0 – 0 0 1 1 1 1 0 0 2 0 0 1 0 3 0 0 0 1 The initial status of the D flip-flops in the absence of clock signal is $\mathrm{Q_{2}Q_{1}Q_{0} \: = \: 001}$. This status repeats for every three positive edge transitions of clock signal. Therefore, the following operations take place for every positive edge of clock signal. Serial input of first D flip-flop gets the previous output of third flip-flop. So, the present output of first D flip-flop is equal to the previous output of third flip-flop. The previous outputs of first and second D flip-flops are right shifted by one bit. That means, the present outputs of second and third D flip-flops are equal to the previous outputs of first and second D flip-flops. Johnson Ring Counter The operation of Johnson Ring counter is similar to that of Ring counter. But, the only difference is that the complemented output of rightmost D flip-flop is given as input of leftmost D flip-flop instead of normal output. Therefore, ‘N’ bit Johnson Ring counter produces a sequence of states (pattern of zeros and ones) and it repeats for every ‘2N’ clock cycles. Johnson Ring counter is also called as Twisted Ring counter and switch tail Ring counter. The block diagram of 3-bit Johnson Ring counter is shown in the following figure. The 3-bit Johnson Ring counter also contains only a 3-bit SIPO shift register. The complemented output of rightmost D flip-flop is connected to serial input of left most D flip-flop. Assume, initially all the D flip-flops are cleared. So, $\mathrm{Q_{2}Q_{1}Q_{0} \: = \: 000}$. Here, $\mathrm{Q_{2}}$ & $\mathrm{Q_{0}}$ are MSB & LSB respectively. We can understand the working of Johnson Ring counter from the following table. No of positive edge of Clock Serial Input = Q0 Q2(MSB) Q1 Q0(LSB) 0 – 0 0 0 1 1 1 0 0 2 1 1 1 0 3 1 1 1 1 4 0 0 1 1 5 0 0 0 1 6 0 0 0 0 The initial status of the D flip-flops in the absence of clock signal is $\mathrm{Q_{2}Q_{1}Q_{0} \: = \: 000}$. This status repeats for every six positive edge transitions of clock signal. Therefore, the following operations take place for every positive edge of clock signal. Serial input of first D flip-flop gets the previous complemented output of third flip-flop. So, the present output of first D flip-flop is equal to the previous complemented output of third flip-flop. The previous outputs of first and second D flip-flops are right shifted by one bit. That means, the present outputs of second and third D flip-flops are equal to the previous outputs of first and second D flip-flops. Print Page Previous Next Advertisements ”;

Binary to Decimal Converter ”; Previous Next A type of code converter used to convert data from binary format to decimal format is called a binary-to-decimal converter. The input to the binary-to-decimal converter is a number represented in a format of 0s and 1s. Then, the converter uses an algorithm to convert the input binary number into an equivalent decimal number. Finally, it generates a decimal code as output. Let us now understand the logic circuit implementation of a binary-to-decimal converter. The truth table of a two-bit binary-to-decimal converter is given below. Binary Input Decimal Output B1 B0 0 0 Q0 0 1 Q1 1 0 Q2 1 1 Q3 Let us now derive the logical expression for each of the decimal outputs. $$\mathrm{Q_{0} \: = \: \overline{B_{1}}\: cdot \:\overline{B_{0}}}$$ $$\mathrm{Q_{1} \: = \: \overline{B_{1}}\: cdot \: B_{0}}$$ $$\mathrm{Q_{2} \: = \: B_{1} \: cdot \:\overline{B_{0}}}$$ $$\mathrm{Q_{3} \: = \: B_{1} \: cdot \: B_{0}}$$ The logic circuit diagram of the binary-to-decimal converter is shown in the following figure. This circuit converts a 2-bit binary number into an equivalent decimal number. However, we can implement the binary-to-decimal converter for any number of bits in the same way. Print Page Previous Next Advertisements ”;

Implementation of OR Gate from NAND Gate ”; Previous Next NAND Gate is a universal logic gate, using which we can realize any logic gate. Read this tutorial to find out how you can realize an OR gate using a NAND gate. Before going into the implementation part, let”s have a brief overview of OR and NAND gates. What is an OR Gate? An OR Gate is a basic logic gate. An OR gate may accept two or more than two inputs, but gives only one output. The OR gate gives a HIGH (Logic 1) output if any one of its inputs is in the HIGH or Logic 1 state, otherwise, it gives a LOW (Logic 0) state as output. Therefore, the output of the OR gate is LOW or Logic 0 state, only if its all inputs are LOW or Logic 0 state. The OR gate is also known as an “any or all gate” or “an inclusive OR gate”. The logic symbol of a two input OR gate is shown in Figure-1. Output Equation of OR Gate If A and B are the input variables and Y is the output variable, then the output equation of the OR gate is given by, $$\mathrm{Y \: = \: A \: + \: B}$$ Where, the ”+” symbol represents the OR operation. It is read as Y is equal to A OR B. Truth Table of OR Gate The table that shows the relationship between inputs and output of a logic gate is referred to as a Truth Table. The following is the truth table for the OR Gate − Input Output A B Y = A + B 0 0 0 0 1 1 1 0 1 1 1 1 What is a NAND Gate? The NAND Gate is a type of universal logic gate. Where, a universal logic gate is one that can be used to realize any kind logical expression or any other type of logic gate. A NAND gate is basically a combination of two basic logic gates namely AND gate and NOT gate, i.e., $$\mathrm{NAND \: Logic \: = \: AND \: Logic \: + \: NOT \: Logic}$$ A NAND gate is the type of logic gate whose output is LOW (Logic 0) when all its inputs are high, and its output is HIGH (Logic 1), when any of its inputs is LOW (Logic 0). Therefore, the operation of the NAND gate is opposite that of the AND gate. The logic symbol of a two input NAND gate is shown in Figure-2. Output Equation of NAND Gate If A and B are the input variables and Y is the output variable of the NAND gate, then its output is given by, $$\mathrm{Y \: = \: \overline{A \: \cdot \: B} \: = \: (A \: \cdot \: B)”}$$ It is read as “Y is equal to A.B whole bar”. Truth Table of NAND Gate The following is the truth table of the NAND gate − Input Output A B Y = (A·B)” 0 0 1 0 1 1 1 0 1 1 1 0 Now, let us discuss the implementation of OR Gate from NAND Gate. Implementation of OR Gate from NAND Gate The NAND gate is a universal gate, therefore, it can be used to realize the OR gate. The implementation of OR gate using the NAND gate is shown in Figure-3. The NAND circuit shown in Figure-3 is equivalent to an OR gate. It is also known as bubbled NAND Gate, where the bubbled NAND gate is equivalent to the OR gate in operation. Theory of OR Gate using NAND Gate To realize the OR gate using NAND gate, we first complement the inputs A and B. This is done by the NAND Gate 1 and 2 in the above Figure-3. Then, these complemented inputs, i.e. A” and B” are applied to a NAND Gate (NAND Gate 3). Thus, we get, $$\mathrm{Y \: = \: \overline{\bar{A} \: \cdot \: \bar{B}}}$$ Using De Morgen”s Law, we have, $$\mathrm{Y \: = \: \bar{\bar{A}} \: + \: \bar{\bar{B}} \: = \: A \: + \: B}$$ This is the output equation of the OR gate. Therefore, the logic circuit of NAND gates in Figure-3 is equivalent to the OR Gate. Print Page Previous Next Advertisements ”;

Binary to Gray Code Converter ”; Previous Next A binary-to-gray code converter is a type of code converter that can translate a binary code into its equivalent gray code. The binary-to-gray code converter accepts a binary number as input and produces a corresponding gray code as output. Here is the truth table explaining the operation of a 4-bit binary-to-gray code converter. Binary Code Gray Code B3 B2 B1 B0 G3 G2 G1 G0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0 Let us derive the Boolean expressions for the gray code output bits. For this, we will simplify the truth table using the K-map technique. K-Map for Gray Code Bit G0 The K-Map simplification to obtain the Boolean expression for the gray code bit G0 is shown in the following figure. Hence, the Boolean expression for the gray code bit G0 is, $$\mathrm{G_{0} \: = \: \overline{B_{1}} \: B_{0} \: + \ B_{1} \: \overline{B_{0}} \: = \: B_{0} \: \oplus \: B_{1}}$$ K-Map for Gray Code Bit G1 The K-Map simplification for the gray code bit G1 is shown below − Thus, the Boolean expression for the gray code bit G1 is, $$\mathrm{G_{1} \: = \: \overline{B_{2}} \: B_{1} \: + \ B_{2} \: \overline{B_{1}} \: = \: B_{1} \: \oplus \: B_{2}}$$ K-Map for Gray Code Bit G2 The K-Map simplification for the gray code bit G2 is depicted in the following figure − The Boolean expression for the gray code bit G2 will be, $$\mathrm{G_{2} \: = \: \overline{B_{3}} \: B_{2} \: + \ B_{3} \: \overline{B_{2}} \: = \: B_{2} \: \oplus \: B_{3}}$$ K-Map for Gray Code Bit G3 The K-Map simplification for the gray code bit G3 is shown in the following figure − Hence, the Boolean expression for the gray code bit G3 is, $$\mathrm{G_{3} \: = \: B_{3}}$$ Let us now utilize these Boolean expressions to implement the logic circuit of the binary-to-gray code converter. The following figure shows the logic circuit diagram of a 4-bit binary code to gray code converter − This circuit can convert a 4-bit binary number into an equivalent gray code. We can follow the same procedure to design a binary-to-gray code converter for any number of bits. Print Page Previous Next Advertisements ”;