Category: digital-electronics

Digital Electronics – Flip-Flops ”; Previous Next A flip-flop is a sequential digital electronic circuit having two stable states that can be used to store one bit of binary data. Flip-flops are the fundamental building blocks of all memory devices. Types of Flip-Flops S-R Flip-Flop J-K Flip-Flop D Flip-Flop T Flip-Flop S-R Flip-Flop This is the simplest flip-flop circuit. It has a set input (S) and a reset input (R). When in this circuit when S is set as active, the output Q would be high and the Q” will be low. If R is set to active then the output Q is low and the Q” is high. Once the outputs are established, the results of the circuit are maintained until S or R get changed, or the power is turned off. Truth Table of S-R Flip-Flop S R Q State 0 0 0 No Change 0 1 0 Reset 1 0 1 Set 1 1 X Characteristics Table of S-R Flip-Flop S R Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 X 1 1 1 X Characteristics Equation of S-R Flip-Flop $$\mathrm{Q(t \: + \: 1) \: = \: S \: + \: R” \: Q(t)}$$ J-K Flip-Flop Because of the invalid state corresponding to S=R=1 in the SR flip-flop, there is a need of another flip-flop. The JK flip-flop operates with only positive or negative clock transitions. The operation of the JK flip-flop is similar to the SR flip-flop. When the input J and K are different then the output Q takes the value of J at the next clock edge. When J and K both are low then NO change occurs at the output. If both J and K are high, then at the clock edge, the output will toggle from one state to the other. Truth Table of JK Flip-Flop J K Q State 0 0 0 No Change 0 1 0 Reset 1 0 1 Set 1 1 Toggles Toggle Characteristics Table of JK Flip-Flop J K Q(t) Q(t+1) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 Characteristics Equation of JK Flip-Flop $$\mathrm{Q(t \: + \: 1) \: = \: j \: k \: Q(t)” \: + \: K”Q(t)}$$ D Flip-Flop In a D flip-flop, the output can only be changed at positive or negative clock transitions, and when the inputs changed at other times, the output will remain unaffected. The D flip-flops are generally used for shift-registers and counters. The change in output state of D flip-flop depends upon the active transition of clock. The output (Q) is same as input and changes only at active transition of clock Truth Table of D Flip-Flop D Q 0 0 1 1 Characteristics Equation of D Flip-Flops $$\mathrm{Q(t \: + \: 1) \: = \: D}$$ T Flip-Flop A T flip-flop (Toggle Flip-flop) is a simplified version of JK flip-flop. The T flop is obtained by connecting the J and K inputs together. The flip-flop has one input terminal and clock input. These flip-flops are said to be T flip-flops because of their ability to toggle the input state. Toggle flip-flops are mostly used in counters. Truth Table of T Flip-Flop T Q(t) Q(t+1) 0 0 0 0 1 1 1 0 1 1 1 0 Characteristics Equation of T Flip-Flop $$\mathrm{Q(t \: + \: 1) \: = \: T”Q(t) \: + \: TQ(t)” \: = \: T \: \oplus \: Q(t)}$$ Applications of Flip-Flops Counters Shift Registers Storage Registers, etc. Print Page Previous Next Advertisements ”;

CPU Architecture ”; Previous Next Microprocessing unit is synonymous to central processing unit, CPU used in traditional computer. Microprocessor (MPU) acts as a device or a group of devices which do the following tasks. Communicate with peripherals devices Provide timing signal Direct data flow Perform computer tasks as specified by the instructions in memory 8085 Microprocessor The 8085 microprocessor is an 8-bit general purpose microprocessor which is capable to address 64k of memory. This processor has forty pins, requires +5 V single power supply and a 3-MHz single-phase clock. Block Diagram ALU The ALU perform the computing function of microprocessor. It includes the accumulator, temporary register, arithmetic & logic circuit & and five flags. Result is stored in accumulator & flags. Block Diagram Accumulator It is an 8-bit register that is part of ALU. This register is used to store 8-bit data & in performing arithmetic & logic operation. The result of operation is stored in accumulator. Diagram Flags Flags are programmable. They can be used to store and transfer the data from the registers by using instruction. The ALU includes five flip-flops that are set and reset according to data condition in accumulator and other registers. S (Sign) flag − After the execution of an arithmetic operation, if bit D7 of the result is 1, the sign flag is set. It is used to signed number. In a given byte, if D7 is 1 means negative number. If it is zero means it is a positive number. Z (Zero) flag − The zero flag is set if ALU operation result is 0. AC (Auxiliary Carry) flag − In arithmetic operation, when carry is generated by digit D3 and passed on to digit D4, the AC flag is set. This flag is used only internally BCD operation. P (Parity) flag − After arithmetic or logic operation, if result has even number of 1s, the flag is set. If it has odd number of 1s, flag is reset. C (Carry) flag − If arithmetic operation result is in a carry, the carry flag is set, otherwise it is reset. Register Section It is basically a storage device and transfers data from registers by using instructions. Stack Pointer (SP) − The stack pointer is also a 16-bit register which is used as a memory pointer. It points to a memory location in Read/Write memory known as stack. In between execution of program, sometime data to be stored in stack. The beginning of the stack is defined by loading a 16-bit address in the stack pointer. Program Counter (PC) − This 16-bit register deals with fourth operation to sequence the execution of instruction. This register is also a memory pointer. Memory location have 16-bit address. It is used to store the execution address. The function of the program counter is to point to memory address from which next byte is to be fetched. Storage registers − These registers store 8-bit data during a program execution. These registers are identified as B, C, D, E, H, L. They can be combined as register pair BC, DE and HL to perform some 16 bit operations. Time and Control Section This unit is responsible to synchronize Microprocessor operation as per the clock pulse and to generate the control signals which are necessary for smooth communication between Microprocessor and peripherals devices. The RD bar and WR bar signals are synchronous pulses which indicates whether data is available on the data bus or not. The control unit is responsible to control the flow of data between microprocessor, memory and peripheral devices. PIN Diagram All the signal can be classified into six groups Sr.No Group Description 1 Address bus The 8085 microprocessor has 8 signal line, A15 – A8 which are uni directional and used as a high order address bus. 2 Data bus The signal line AD7 – AD0 are bi-directional for dual purpose. They are used as low order address bus as well as data bus. 3 Control signal and Status signal Control Signal RD bar − It is a read control signal (active low). If it is active then memory read the data. WR bar − It is write control signal (active low). It is active when written into selected memory. Status signal ALE (Address Latch Enable) − When ALE is high. 8085 microprocessor use address bus. When ALE is low. 8085 microprocessor is use data bus. IO/M bar − This is a status signal used to differentiate between i/o and memory operations. When it is high, it indicate an i/o operation and when it is low, it indicate memory operation. S1 and S0 − These status signals, similar to i/o and memory bar, can identify various operations, but they are rarely used in small system. 4 Power supply and frequency signal Vcc − +5v power supply. Vss − ground reference. X, X − A crystal is connected at these two pins. The frequency is internally divided by two operate system at 3-MHz, the crystal should have a frequency of 6-MHz. CLK out − This signal can be used as the system clock for other devices. 5 Externally initiated signal INTR (i/p) − Interrupt request. INTA bar (o/p) − It is used as acknowledge interrupt. TRAP (i/p) − This is non maskable interrupt and has highest priority. HOLD (i/p) − It is used to hold the executing program. HLDA (o/p) − Hold acknowledge. READY (i/p) − This signal is used

Excess-3 to BCD Converter ”; Previous Next An excess-3 to BCD converter is a type of code converter in digital electronics used to translate an XS-3 code into an equivalent binary-coded decimal. Therefore, an XS-3 to BCD code converter accepts a digital code in XS-3 format and produces an equivalent digital code in BCD format. The truth table of the XS-3 to BCD code converter is given below − Excess-3 Code BCD Code X3 X2 X1 X0 B3 B2 B1 B0 0 0 0 0 X X X X 0 0 0 1 X X X X 0 0 1 0 X X X X 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 1 0 1 0 0 1 0 0 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 X X X X 1 1 1 0 X X X X 1 1 1 1 X X X X Now, we will simplify this truth table using K-map method to obtain the Boolean expression for the output bits. K-Map for BCD Bit B0 The following figure shows the K-map simplification for the BCD bit B0. This K-map gives the following Boolean expression, $$\mathrm{B_{0} \: = \: \overline{X_{0}}}$$ K-Map for BCD Bit B1 The following figure shows the K-map simplification for the BCD bit B1. This K-map gives the following Boolean expression, $$\mathrm{B_{1} \: = \: \overline{X_{1}} \: X_{0} \: + \: X_{1} \: X_{0}}$$ K-Map for BCD Bit B2 The K-map simplification for the BCD bit B2 is shown below − The simplification of this K-map gives the following Boolean expression, $$\mathrm{B_{2} \: = \: \overline{X_{2}} \: \overline{X_{1}} \: + \: \overline{X_{2}} \: \overline{X_{0}} \: + \: X_{2} \: X_{1} \: X_{0}}$$ K-Map for BCD Bit B3 The K-map simplification for the BCD bit B3 is shown in the following figure − By simplifying this K-map, we obtain the following Boolean expression, $$\mathrm{B_{3} \: = \: X_{3} \: X_{2} \: + \: X_{3} \: X_{1} \: X_{0}}$$ We can use these Boolean expressions to implement the digital logic circuit to perform the XS-3 to BCD conversion. The logic circuit diagram to convert an XS-3 code into equivalent BCD code i.e., Excess-3 to BCD converter is shown in the following figure − This is all about some commonly used digital code converters used in various digital electronic applications. Print Page Previous Next Advertisements ”;

RAM and ROM ”; Previous Next In the last chapter, we had a discussion on memory devices and their characteristics. Read this chapter to understand the characteristics of the two most important types of memories named, RAM (Random Access Memory) and ROM (Read Only Memory) which are used in digital systems like computer, laptops, smartphones, etc. What is RAM? A RAM constitutes the internal memory of the CPU for storing data, program and program result. It is read/write memory. It is called Random Access Memory (RAM). Since the access time in RAM is independent of the address to the word that is, each storage location inside the memory is as easy to reach as other location & takes the same amount of time. We can reach into the memory at random & extremely fast but can also be quite expensive. RAM is a volatile memory i.e., data stored in it is lost when we switch off the computer or if there is a power failure. Hence, a backup uninterruptible power system (UPS) is often used with computers. RAM is small, both in terms of its physical size and in the amount of data it can hold. Types of RAM RAM or Random Access Memory is classified into the following two types − Static RAM (SRAM) Dynamic RAM (DRAM) Let’s discuss about these two types of RAMs in detail. Static RAM (SRAM) The word “static” indicates that the memory retains its contents as long as power remains applied. However, data is lost when the power gets down due to volatile nature. SRAM chips use a matrix of 6-transistors and no capacitors. Transistors do not require power to prevent leakage, so SRAM need not have to be refreshed on a regular basis. Because of the extra space in the matrix, SRAM uses more chips than DRAM for the same amount of storage space, thus making the manufacturing costs higher. Static RAM is mainly used as cache memory needs to be very fast and small. Characteristics of SRAM The following are some important characteristics of SRAM − Being a type of RAM, the SRAM is also a volatile memory. Thus, it requires a continuous power supply to maintain its stored data. If power supply is removed or switched off, the data stored in the SRAM will delete. SRAM is a high-speed random access memory. SRAM does not need to be refreshed to maintain its stored data. SRAM is made up of semiconductor components called flip-flops which store data. SRAM has lower storage density. This is mainly because of its complex memory cell structure. This also results in larger physical size. SRAM is mostly employed in digital systems in which high-speed data access is important. For example, it is used as CPU cache memory, high-speed buffers, and registers in microprocessors and microcontrollers. SRAM is relatively more expensive. This is mainly because of its lower storage density and higher manufacturing cost. Dynamic RAM (DRAM) DRAM, unlike SRAM, must be continually refreshed in order for it to maintain the data. This is done by placing the memory on a refresh circuit that rewrites the data several hundred times per second. DRAM is used for most system memory because it is cheap and small. All DRAMs are made up of memory cells. These cells are composed of one capacitor and one transistor. Characteristics of DRAM The important characteristics of DRAM (Dynamic Random Access Memory) are listed below − Since DRAM is also a random access memory, hence it is also a volatile memory and thus requires a continuous power supply to retain its stored data. The data stored in DRAM is lost, when power supply to is turned off. In DRAM, the memory cells are made up of capacitors and transistors. Where each memory cell can store a 1-bit of data in the form electric charge in a capacitor. In DRAM, to prevent losing stored data due to leakage in capacitor, a refresh circuit is required for periodic refresh cycles. This is the primary reason the term “dynamic” is used in DRAM. For DRAM, the access time is typically of the order in nanoseconds (ns). DRAM is less expensive than SRAM. This is all about RAM (Random Access Memory) and its types. Let us now discuss about another type of memory device called ROM. What is ROM? ROM stands for Read Only Memory. The memory from which we can only read but cannot write on it. This type of memory is non-volatile. The information is stored permanently in such memories during manufacture. A ROM, stores such instruction as are required to start computer when electricity is first turned on, this operation is referred to as bootstrap. ROM chip are not only used in the computer but also in other electronic items like washing machine and microwave oven. Types of ROM The following are some important types of Read Only Memory (ROM) − MROM PROM EPROM EEPROM Let’s discuss these different types of ROMs in detail along with their important characteristics. MROM (Masked ROM) The very first ROMs were hard-wired devices that contained a pre-programmed set of data or instructions. These kinds of ROMs are known as Masked ROMs. It is inexpensive ROM. Since it is a type of ROM, thus it is also a non-volatile memory. The MROMs are programmed at the time of manufacturing and its data cannot be modified or changed at a later point of time. Characteristics of MROM The following are some important characteristics of MROM − MROM is a non-volatile memory. Hence, it can retain its data even when power supply is turned off or removed. MROM is mainly used

Implementation of NOT Gate from NOR Gate ”; Previous Next A NOT Gate is a basic logic gate that gives an output which is complement of its input. A NOR gate is a universal logic gate that can be used to implement any other type of logic gate. A NOR gate is basically an OR gate followed by a NOT gate. Read this tutorial to find out how you can implement a NOT gate using NOR gate. Let”s start the discussion with a brief overview of NOT and NOR gates. What is a NOT Gate? In digital electronics, a NOT gate is a basic logic gate that has only one input and one output. It is type of logic gate whose output is always the complement of its input. Therefore, the NOT gate is also known as an inverter. If the input of the NOT gate is LOW (Logic 0), then it gives an output that is HIGH (Logic 1). If the input is HIGH (Logic 1), then the NOT gate gives the LOW (logic 0) output. The logic symbol of the NOT gate is shown in Figure-1. The NOT operation is represented by the ”-” (bar) symbol. Therefore, if the input variable of the NOT gate is A, then its output Y is given by, $$\mathrm{Y \: = \: \bar{A} \: = \: A” }$$ Truth Table of NOT Gate The truth table of the NOT gate gives the relationship between its input variable and output variable. The following is truth table of the NOT gate − Input (A) Output (Y = A”) A B 0 1 1 0 What is a NOR Gate? NOR gate is a type of universal gate, therefore, it can be used to implement any other type of logic gate. NOR gate is basically a combination of NOT gate and OR gate, i.e. OR gate followed by a NOT gate is a NOR gate. Thus, $$\mathrm{NOR \: Gate \: = \: OR \: Gate \: = \: NOT \: Gate}$$ A NOR gate can accept any number of inputs and gives a single output. The output of the NOR gate is assumed HIGH or Logic 1, only when all of its inputs are LOW or Logic 0. For any other combination of inputs, the output of the NOR gate is assumed LOW or Logic 0. The logic symbol of a two input NOR gate is shown in Figure-2. The operation of the NOR Gate is expressed by, $$\mathrm{Y \: = \: \overline{A \: + \: B} \: = \: (A \: + \: B)”}$$ Where, A and B are the input variables and Y is the output variable of the NOR gate. The output expression of the NOR gate is read as “Y is equal to A plus B whole bar”. Truth Table of NOR Gate For different combinations of inputs, we can analyze the operation of the NOR gate using its truth table, which is given below. Input Output A B Y = (A + B)” 0 0 1 0 1 0 1 0 0 1 1 0 Now, let us discuss the implementation of NOT Gate using NOR Gate. Implementation of NOT Gate from NOR Gate As discussed above, a NOR gate is a universal gate, therefore, we can use it to realize any other type of logic gate. The implementation of NOT gate from NOR gate is shown in Figure-3. Hence, to realize the NOT gate using NOR gate, we simply join all its inputs terminals together and apply the signal to be NOTed or inverted to this common input terminal. Also, we can use the NOR gate as a NOT gate by connecting all its input terminals except one to Logic 0, and applying the signal to be inverted to the remaining terminal. This configuration of NOR Gate as NOT Gate is referred to as a controlled inverter. Hence, in this way, the NOT gate can be implemented using a NOR gate only. Print Page Previous Next Advertisements ”;

Programmable Logic Devices ”; Previous Next Programmable Logic Devices (PLDs) are a collection of integrated circuits which are configured to perform various logical functions. PLDs play an important role in the field of engineering and technology, as they form the basis of innovation and support engineers to develop automated digital systems to improve process flexibility and efficiency. Here, “programmable” means defining a function that can be performed multiple times without human intervention. Programmable Logic Devices (PLDs) are the integrated circuits. They contain an array of AND gates & another array of OR gates. There are three kinds of PLDs based on the type of array(s), which has programmable feature. Programmable Read Only Memory Programmable Array Logic Programmable Logic Array The process of entering the information into these devices is known as programming. Basically, users can program these devices or ICs electrically in order to implement the Boolean functions based on the requirement. Here, the term programming refers to hardware programming but not software programming. In this chapter, we will explain the basic concepts of programmable logic devices, their types, advantages, limitations, and applications. Programmable Read Only Memory (PROM) Read Only Memory (ROM) is a memory device, which stores the binary information permanently. That means, we can’t change that stored information by any means later. If the ROM has programmable feature, then it is called as Programmable ROM (PROM). The user has the flexibility to program the binary information electrically once by using PROM programmer. PROM is a programmable logic device that has fixed AND array & Programmable OR array. The block diagram of PROM is shown in the following figure. Here, the inputs of AND gates are not of programmable type. So, we have to generate 2n product terms by using 2n AND gates having n inputs each. We can implement these product terms by using nx2n decoder. So, this decoder generates ‘n’ min terms. Here, the inputs of OR gates are programmable. That means, we can program any number of required product terms, since all the outputs of AND gates are applied as inputs to each OR gate. Therefore, the outputs of PROM will be in the form of sum of min terms. Example Let us implement the following Boolean functions using PROM. $$\mathrm{A(X,Y,Z):=:sum mleft ( 5,6,7 right )}$$ $$\mathrm{B(X,Y,Z):=:sum mleft ( 3,5,6,7 right )}$$ The given two functions are in sum of min terms form and each function is having three variables X, Y & Z. So, we require a 3 to 8 decoder and two programmable OR gates for producing these two functions. The corresponding PROM is shown in the following figure. Here, 3 to 8 decoder generates eight min terms. The two programmable OR gates have the access of all these min terms. But, only the required min terms are programmed in order to produce the respective Boolean functions by each OR gate. The symbol ‘X’ is used for programmable connections. What is a Programmable Logic Device? A Programmable Logic Device (PLD) can be defined as an integrated circuit (IC) which can be programmed to perform specific functions. Here, programming means we can define a set of instructions that can be executed to perform the functions multiple times without need of any human intervention. The primary need of developing PLDs is occurred to implement digital logic functions that can copy the behavior of conventional logic circuits and replicate it many times. However, the PLDs are different from normal digital logic circuits in terms of programmability, which means we can define the desired logic functions by setting a collection of instructions in the device. Types of PLDs Based on the type of device used, Programmable Logic Devices (PLDs) can be classified into the following two types − Bipolar PLDs CMOS PLDs Let us discuss each type of programmable logic device in detail. Bipolar PLDs Bipolar PLDs are the types of programmable logic devices in which Bipolar Junction Transistor (BJT) is the main functional device. Bipolar PLDs are the older versions of programmable logic devices. Thus, they were commonly used before the development of CMOS PLDs. The following are some important characteristics of the bipolar programmable logic devices − Bipolar PLDs provide fast switching speeds and hence they can operate at higher frequencies. Bipolar PLDs are better suited for applications involving rapid signal processing and require fast response times. Bipolar PLDs require more power to operate. Bipolar PLDs have better immunity to electronic noise and interference. All these characteristics make the bipolar programmable logic devices well-suited to use in the applications where high-speed operation and reliability are critical, such as aerospace, military, and telecommunications systems. CMOS PLDs CMOS PLDs stand for Complementary Metal Oxide Semiconductor Programmable Logic Devices. As their name implies, CMOS PLDs use the CMOS transistors i.e., NMOS (N-channel Metal Oxide Semiconductor) and PMOS (P-channel Metal Oxide Semiconductor) transistors as the fundamental component. CMOS PLDs are basically the modern versions of PLDs and are widely used in modern digital systems due to their numerous advantages. Some important characteristics of CMOS PLDs are described below − CMOS PLDs require very less amount of power to operate. Hence, this characteristic makes the CMOS PLDs well-suited to use in battery-power devices where energy efficiency is an important factor. CMOS PLDs are more reliable and robust. As they are designed to withstand against various environmental factors like high/low temperatures, voltage fluctuations, and different radiation interferences. CMOS PLDs are also excellent in terms of scalability. CMOS PLDs are newer PLD devices and hence are very commonly used in various modern electronics devices like consumer electronics, medical equipment, industrial automation systems, automotive systems. PLD Programming Languages In the case of programmable logic

Implementation of NOT Gate using NAND Gate ”; Previous Next Before getting into implementing a NOT gate using NAND gate, let’s have a basic overview of NOT gates and NAND gates. What is NOT Gate? NOT gate is a basic logic gate used in digital electronic circuits. The NOT gate has a single input and a single output. The output of the NOT gate is the logical inversion of its input. For this reason, the NOT gate is also known as inverter. The symbol of the standard NOT gate has a triangle pointing to the right with a circle at its right end as shown in figure-1. This circle is referred to as an inversion bubble. The NOT gate produces an output which is the complement or inversion of its input. For example, if we give a HIGH input single, then it provides a LOW output signal. Similarly, when we give a LOW input signal, then it provides a HIGH output signal. Since, the NOT gate is a single input device, therefore, it is not used as a decision making component in the logic circuits. Truth Table of NOT Gate The following is the truth table of NOT gate − Input (A) Output (Y = A’) 0 1 1 0 Boolean Expression of NOT Gate The following is the Boolean expression of the NOT gate − $$\mathrm{Y \: = \: A”}$$ For a NOT gate, if A is 1 (HIGH / TRUE), then Y is 0 (LOW / FALSE), and vice-versa. What is NAND Gate? NAND is a universal logic gate. It is a digital logic gate having two or more input terminals and gives an output depending on the combination of the input signals. NAND represents NOT + AND, i.e. it produces an output which is the inversion or compliment of logic AND operation. Since, NAND is a universal logic gate, therefore, it can be used to implement all kinds of logic operations like OR, AND, NOT. The symbol of the NAND gate is shown in Figure-2. From the symbol, it is clear that it has a shape of standard AND gate with a circle. This circle is known as inversion bubble. The symbol gives the idea about the operation of the NAND gate, i.e. it takes inputs, performs AND operations, and at last takes the inversion of the result of AND operation to provide the final output of the NAND gate. Truth Table of NAND Gate The following is the truth table of the NAND gate − Inputs Output A B Y = (AB)’ 0 0 1 0 1 1 1 0 1 1 1 0 From the truth table of NAND gate, it is clear that the operation of the NAND gate is same as that of the AND gate followed by a NOT gate. For this reason, the symbol of the NAND is like as shown in the Figure-2. Boolean Expression of NAND Gate The following is the Boolean expression of the NAND gate − $$\mathrm{Y \: = \: (AB)”}$$ Now, let us discuss the implementation of NOT gate using NAND gate. Implementation of NOT Gate using NAND Gate As we discussed in the above section that the NAND gate is a universal gate, thus we can use it to realize any basic logic gate. The realization of NOT gate using NAND gate is shown in Figure-3. From Figure-3, it is clear that to realize the NOT gate using the NAND gate, we have to join the two input terminals of the NAND gate to form a single input terminal of the NOT gate, and the output of the NOT gate is taken from the output terminal of the NAND gate. Truth Table of NOT Gate using NAND Gate The following is the truth table of NOT gate using NAND gate − Inputs Output A B Y = (AB)’ = A’ 0 0 1 1 1 0 Hence, this is all about the implementation of NOT gate using NAND gate. Print Page Previous Next Advertisements ”;

Implementation of AND Gate from NAND Gate ”; Previous Next As we know that the NAND Gate is a universal logic gate, therefore using the NAND gate, we can implement any logic gate or any other logical expression. Read this tutorial to understand how you can implement an AND gate using NAND gate. Let”s start with a basic overview of AND and NAND gates. What is an AND Gate? An AND Gate is a basic logic gate. An AND gate may have two or more than two inputs, but gives only one output. The AND gate gives a LOW (Logic 0) output if any one of its inputs is in the LOW or Logic 0 state, otherwise, it gives a HIGH (Logic 1) state as output. Therefore, the output of the AND gate is HIGH or Logic 1 state, only if all its inputs are HIGH or Logic 1 state. The AND gate is also known as an “all or nothing gate”. The logic symbol of a two input AND gate is shown in Figure-1. Output Equation of AND Gate If A and B are the input variables and Y is the output variable for an AND gate, then the output equation of the AND gate is given by, $$\mathrm{Y \: = \: Acdot B}$$ Where, the “·” (dot) symbol represents the AND operation. It is read as Y is equal to A AND B. Truth Table of AND Gate The table that show the relationship between inputs and output of a logic gate is referred to as a truth table. The following is the truth table for the AND Gate − Input Output A B Y = A · B 0 0 0 0 1 0 1 0 0 1 1 1 What is a NAND Gate? The NAND Gate is a type of universal logic gate. Where, a universal logic gate is one that can be used to realize any kind logical expression or any other type of logic gate. A NAND gate is basically a combination of two basic logic gates namely AND gate and NOT gate, i.e. $$\mathrm{NAND \: Logic \: = \: AND \: Logic \: + \: NOT \: Logic}$$ A NAND gate is the type of logic gate whose output is LOW (Logic 0) when all its inputs are high, and its output is HIGH (Logic 1), when any of its inputs is LOW (Logic 0). Therefore, the operation of the NAND gate is opposite that of the AND gate. The logic symbol of a two input NAND gate is shown in Figure-2. Output Equation of NAND Gate If A and B are the input variables and Y is the output variable of the NAND gate, then its output is given by, $$\mathrm{Y | \: = \: \overline{A \: \cdot \: B} \: = \: (\arrowvert A \: \cdot \: B)”}$$ It is read as “Y is equal to A·B whole bar”. Truth Table of NAND Gate The following is the truth table of the NAND gate − Input Output A B Y = (A · B)” 0 0 1 0 1 1 1 0 1 1 1 0 Now, let us discuss the implementation of AND Gate from NAND Gate. Implementation of AND Gate from NAND Gate As discussed above that the NAND gate is a type of universal logic gate, because it can be used to implement any other logic gate. The implementation of an AND gate using NAND gate is shown in Figure-3. From this circuit diagram, it is clear that the implementation of the AND gate from NAND gate is quite simple, as we just require two NAND gates. Where, the first NAND gate produce a complement binary product of inputs A and B, while the second NAND gate again complement the output of first NAND gate to produce an AND output. Therefore, the logic circuit using NAND gates shown in figure-3 is equivalent to the AND gate. Output Equation The output produced by the first NAND gate is, $$\mathrm{Y_{1} \: = \: \overline{A \: \cdot \: B}}$$ The output produced by the second NAND gate is, $$\mathrm{Y \: = \: \overline{\overline{A \: \cdot \: B}} \: = \: A \: \cdot \: B}$$ This is the output equation of the AND gate. Print Page Previous Next Advertisements ”;

Full Subtractor in Digital Electronics ”; Previous Next What is a Full-Subtractor? A full-subtractor is a combinational circuit that has three inputs A, B, bin and two outputs d and b. Where, A is the minuend, B is subtrahend, bin is borrow produced by the previous stage, d is the difference output and b is the borrow output. As we know that the half-subtractor can only be used for subtraction of LSB (least significant bit) of binary numbers. If there is any borrow during the subtraction of the LSBs of two binary numbers, then it will affect the subtraction of next stages. Therefore, the subtraction with borrow are performed by a full subtractor. The block diagram and circuit diagram of a full-subtractor is shown in Figure-1. Therefore, we can realize the full-subtractor using two XOR gates, two NOT gates, two AND gates, and one OR gate. Operation of Full Subtractor Now, let us understand the operation of the full subtractor. Full subtractor performs its operation to find the difference of two binary numbers according to the rules of binary subtraction, which are as follows − In the case of full subtractor, the 1s and 0s for the output variables (difference and borrow) are determined from the subtraction of A – B – bin. From the logic circuit diagram of the full subtractor, it is clear that the difference bit (d) is obtained by the XOR operation of the two inputs A, B, and bin, and the output borrow bit (b) is obtained by NOT, AND, and OR operations of variable A, B, and bin. Truth Table of Full-Subtractor The truth table is one that gives relationship between input and output of a logic circuit. The following is the truth table of the full-subtractor − Inputs Outputs A B Bin D (Difference) B (Borrow) 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 K-Map for Full Subtractor We can use the K-Map (or Karnaugh Map), a method for simplifying Boolean algebra, to determine equations of the difference bit (d) and the output borrow bit (b). The K-Map simplification for half subtractor is shown in Figure-2. Characteristic Equations of Full Subtractor The characteristic equations of the full subtractor, i.e. equations of the difference (d) and borrow output (b) are obtained by following the rules of binary subtraction. These equations are given below − The difference (d) of the full subtractor is the XOR of A, B, and bin. Therefore, $$\mathrm{Difference, \: d \: = \: A \oplus B \oplus b_{in} \: = \: A”B”b_{in} \: + \: AB”b”_{in} \: + \: A”Bb”_{in} \: + \: ABb_{in}}$$ The borrow (b) of the full subtractor is given by, From the logic circuit diagram and k-map − $$\mathrm{Borrow, \: b \: = \: A”B \: + \: \left ( A \oplus B \right ) \: ”b_{in}}$$ From Truth Table $$\mathrm{Borrow, \: b \: = \: A”B”b_{in} \: + \: A”Bb”_{in} \: + \: A”Bb_{in} \: + \: ABb_{in}}$$ Or $$\mathrm{Borrow, \: b \: = \: A”B \left ( b_{in} \: + \: b”_{in} \right ) \: + \: \left (AB \: + \: A”B” \right )b_{in} \: = \: A”B \: + \: \left (A \oplus B \right )”b_{in}}$$ Applications of Full Subtractor The following are some important applications of full subtractor − Full subtractors are used in ALU (Arithmetic Logic Unit) in computers CPUs. Full subtractors are extensively used to perform arithmetical operations like subtraction in electronic calculators and many other digital devices. Full subtractors are used in different microcontrollers for arithmetic subtraction. They are used in timers and program counters (PC). Full subtractors are also used in processors to compute addresses, tables, etc. Full subtractors are also used in DSP (Digital Signal Processing) and networking based systems. Conclusion From the above discussion, we can conclude that a full-subtractor is a combinational logic circuit that can compute the difference of three binary digits. In a full subtractor, the borrow (if any) from the previous stage is also used in subtraction operation in the next stages. Therefore, full subtractors are used to perform subtraction of binary numbers having any number of digits. Print Page Previous Next Advertisements ”;

Parallel Adder and Parallel Subtractor ”; Previous Next In digital electronics, adder and subtractor are the two most basic arithmetic combinational circuits. The adder is a combinational arithmetic circuit used to perform addition of two or more binary numbers. Whereas, the subtractor is a combination arithmetic circuit used to perform subtraction of two binary numbers. Depending on the form in which the addition and subtraction of binary numbers are executed, the adder and subtractor are classified into following types − Serial Adder Parallel Adder Serial Subtractor Parallel Subtractor This tutorial is meant for explaining Parallel Adder and Parallel Subtractor. But before that let us first discuss the rules of Boolean algebra followed to perform the binary addition and subtraction. Binary Addition The following rules are followed while performing binary addition − Binary Digit A Binary Digit B Sum (A + B) Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Binary Subtraction The following rules are to be followed while performing binary subtraction − Binary Digit A Binary Digit B Difference (A – B) Borrow 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 Now, let us discuss the parallel adder and parallel subtractor in detail. What is Parallel Adder? A digital circuit that adds two binary numbers of any bit length in parallel form and produces the sum of those number in parallel form is called a parallel adder. A parallel adder basically consists of full adders in a chain form as shown in Figure 1. Here, the output bit of each full adder is connected to the input carry terminal of the next full adder circuit in the chain. The parallel adder shown in Figure 1 is a 4-bit parallel adder as it can add two binary number of 4 bits. Although, we can design a parallel adder circuit for any number of bits by increasing the number of full adders in the chain. In the above parallel adder circuit, the bit A is representing the augend bits and B is representing the addend bits. The first input carry bit to the parallel adder is Cin and the output carry bit of the parallel adder is C4. The output sum bits are designated by S. We can also construct a parallel adder in the form of an IC. For example, when the 4-bit parallel adder is formed in the IC form, then it will have four terminals for augend bits, 4 terminals for addend bits, 4 terminals for sum bits, and 2 terminals for input and output carry bits. Working of Parallel Adder The parallel adder shown in figure-1 performs the binary addition of two numbers as per the following step − Step 1 − Firstly, the full adder circuit FA1 adds the bits A1 and B1 along with the input carry bit Cin to produce the sum bit S1, where it is the LSB (Least Significant Bit) of the output sum. At this stage, a carry bit C1 is generated which is transferred to the next full adder circuit in the chain. Step 2 − The full adder circuit FA2 adds bits A2 and B2 along with the carry bit C1 from the previous addition. It produces the sum bit S2 which is the second bit of the output sum, and a carry bit C2 is also produced which again forwarded to the next full adder FA3. Step 3 − The full adder circuit FA3 adds inputs bits A3 and B3 along with the carry bit C2 from previous addition to produce sum bit S3 and carry bit C3. Step 4 − The full adder FA4 adds input bits A4 and B4 along with the carry bit C3 forward from FA3. It generates the last sum bit S4 and a last carry bit C4. Step 5 − The output sum of the parallel adder is then given by, $$\mathrm{S_{out} \: = \: C_{4} \: S_{4} \: S_{3} \: S_{2} \: S_{1}}$$ What is Parallel Subtractor? A digital arithmetic circuit which is used to find the arithmetic difference of two binary numbers in parallel form is called a parallel subtractor. We can implement a parallel subtractor in several ways such as combining half subtractors and full subtractors, all full subtractors, all full adders, etc. Here, we have realized a 4-bit parallel subtractor using all full adders with subtrahend bit complemented as shown in Figure 2. This is the 4-bit parallel subtractor, however, we can implement a parallel subtractor by adding any number of full adders in the chain of the circuit shown in figure-2. The binary subtraction of two binary numbers can be conveniently accomplished by means of 1”s or 2”s complement. Where, the complement method converts the subtraction operation in simple addition operation. The 2”s complement of binary numbers is obtained by taking the 1”s complement and adding 1 to the least significant pair of bits. The 1”s complement can be implemented with the help of a NOT gate (inverter). Working of Parallel Subtractor The parallel subtractor shown in above figure-2 carries out the subtraction of two binary numbers as per the following steps − Step 1 − Firstly, the 1”s complement of bit B1 obtained using an inverter and a 1 (Cin) are added to obtain the 2”s complement