Category: digital-electronics

Analog to Digital Converter ”; Previous Next An analog-to-digital converter, also known as ADC, is a digital circuit used to convert analog signals into digital format. The conversion of analog signals into digital format is crucial for their processing with the help of digital systems like microprocessors, microcontrollers, digital signal processors (DSPs), etc. Therefore, ADCs are important components in several digital systems like computers and other digital devices. In this chapter, we will explain in detail the concept, components, types, and applications of analog to digital converters. What is an Analog to Digital Converter? An analog to digital converter is a digital circuit designed to perform conversion of analog signals into digital data format. It is also known ADC. Analog to digital converters are essential components in digital systems like computers, data processors, digital communication systems, etc. The following figure depicts the block diagram of an analog to digital converter − From this figure, it is clear that the input to an analog to digital converter is an analog or natural signal and the output is a digital or discrete time signal. In practical systems, the analog to digital converter serves as an interface between external environment and a digital system. Working of Analog to Digital Converter The working of an analog to digital converter involves the processes explained below − Inputting Analog Signal An analog to digital converter takes an analog signal as input. The analog signal could be a voltage, current, temperature, pressure, or any other physical quantity that changes continuously with time. Sampling At this stage, the analog to digital converter samples the input analog signal at regular intervals of time. These time intervals are defined in terms of sampling rate. In the sampling process, the analog signal that varies continuously over time is measured at discrete instants of time to collect discrete values of the signal. Quantization Quantization is a process of assigning a digital or discrete value to each sampled value of the analog signal. In the process of quantization, the range of all possible analog values is divided into a finite number of discrete digital values. Encoding Encoding is a process of converting the quantized digital values into their equivalent binary numbers. These encoded binary numbers represent the sampled analog values in the digital format. The resolution, accuracy, and precision of the analog to digital converter is determined by the number of bits used for encoding. Outputting Digital Signal At the end, the analog to digital converter produces a digital signal as output. This output digital signal can be processed, stored, or transmitted by digital systems. Performance Factors of Analog to Digital Converters The performance of an analog to digital converter can be evaluated using several different factors. The following two are the most important − Signal-to-Noise Ratio (SNR) of ADC The Signal-to-Noise Ratio (SNR) of an analog to digital converter is defined as the measure of ability of the converter to differentiate between the desired signal and unwanted noise signal. Mathematically, the SNR of an analog to digital converter is expressed as the ratio of the power of the electrical signal (that represents the useful information) to the power of the noise signal (that represents the unwanted disturbances). In practice, the SNR is expressed in decibels (dB) and the formula for calculating the SNR of an ADC is given below, $$\mathrm{SNR \: of \: ADC \: = \: 10 \: \times \: log ( \frac{Electrical \: Signal \: Power}{Noise \: Signal \: Power})}$$ From this expression, it is clear that a higher SNR represents better performance of the analog to digital converter. In other words, an analog to digital converter having a high SNR distinguishes the electrical signal from the noise signal more clearly. Therefore, it is desirable that the analog to digital converter have a high SNR so that it can accurately capture and digitalize smaller analog signals even in the presence of noise signals. Bandwidth of Analog to Digital Converter The bandwidth of an analog to digital converter is nothing but the range of frequencies that it can sample and digitalize accurately. The sampling rate of the analog to digital converter determines its bandwidth. Where, the sampling rate is defined as the number of samples of the analog signal taken per second. According to the Nyquist-Shannon sampling theorem, the maximum sampling rate of an analog to digital converter should be at least double of the maximum frequency component present in the input analog signal. It is an important factor to avoid misidentification of the signal that can introduce distortion or error in sampling. Let us take an example to understand this, consider an analog to digital converter having a maximum sampling rate of 150 kHz, then its bandwidth should be limited to frequencies less than 75 kHz to prevent distortion. Hence, it is important that the analog to digital converter should have a sufficient bandwidth to capture the high-frequency analog signals accurately. Types of Analog-to-Digital Converters In digital electronics, different types of analog-to-digital converters (ADCs) are designed to fulfil the requirements of different applications.Some of common types of analog-to-digital converters include the following − Flash ADC Semi-Flash ADC Successive Approximation Register ADC Sigma-Delta ADC Pipelined ADC Flash ADC Flash ADC, also known as Direct ADC, is the fastest ADC available. This type of ADC has sampling rates of the order of gigahertz. The flash ADCs offer such high speeds because they use a bank of comparators that can operate in parallel, each for a certain voltage range. However, the flash ADCs are relatively larger in size and costlier than other types of ADCs. Also, they consume relatively more power. In the case of a flash ADC, if

Full Adder in Digital Electronics ”; Previous Next What is a Full Adder? A combinational logic circuit that can add two binary digits (bits) and a carry bit, and produces a sum bit and a carry bit as output is known as a full-adder. In other words, a combinational circuit which is designed to add three binary digits and produces two outputs (sum and carry) is known as a full adder. Thus, a full adder circuit adds three binary digits, where two are the inputs and one is the carry forwarded from the previous addition. The block diagram and circuit diagram of the full adder are shown in Figure-1. Hence, the circuit of the full adder consists of one EX-OR gate, three AND gates and one OR gate, which are connected together as shown in the full adder circuit in Figure-1. Operation of Full Adder Full adder takes three inputs namely A, B, and Cin. Where, A and B are the two binary digits, and Cin is the carry bit from the previous stage of binary addition. The sum output of the full adder is obtained by XORing the bits A, B, and Cin. While the carry output bit (Cout) is obtained using AND and OR operations. Truth Table of Full Adder Truth table is one that indicates the relationship between input and output variables of a logic circuit and explains the operation of the logic circuit. The following is the truth table of the full-adder circuit − Inputs Outputs A B Cin S (Sum) Cout (Carry) 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Hence, from the truth table, it is clear that the sum output of the full adder is equal to 1 when only 1 input is equal to 1 or when all the inputs are equal to 1. While the carry output has a carry of 1 if two or three inputs are equal to 1. K-Map for Full Adder K-Map (Karnaugh Map) is a tool for simplifying binary complex Boolean algebraic expressions. The K-Map for full adder is shown in Figure-2. Characteristic Equations of Full Adder The characteristic equations of the full adder, i.e. equations of sum (S) and carry output (Cout) are obtained according to the rules of binary addition. These equations are given below − The sum (S) of the full-adder is the XOR of A, B, and Cin. Therefore, $$\mathrm{Sum, \: S \: = \: A \: \oplus \: B \: \oplus \: C_{in} \: = \: A”B”C_{in} \: + \: A”BC”_{in} \: + \: AB”C”_{in} \: + \: ABC_{in} }$$ The carry (C) of the half-adder is the AND of A and B. Therefore, $$\mathrm{Carry, \: C \: = \: AB \: + \: AC_{in} \: + \: BC_{in}}$$ Advantages of Full Adder The following are the important advantages of full adder over half adder − Full adder provides facility to add the carry from the previous stage. The power consumed by the full adder is relatively less as compared to half adder. Full adder can be easily converted into a half subtractor just by adding a NOT gate in the circuit. Full adder produces higher output that half adder. Full adder is one of the essential part of critic digital circuits like multiplexers. Full adder performs operation at higher speed. Applications of Full Adder The following are the important applications of full adder − Full adders are used in ALUs (arithmetic logic units) of CPUs of computers. Full adders are used in calculators. Full adders also help in carrying out multiplication of binary numbers. Full adders are also used to realize critic digital circuits like multiplexers. Full adders are used to generate memory addresses. Full adders are also used in generation of program counterpoints. Full adders are also used in GPU (Graphical Processing Unit). Conclusion In this tutorial, we discussed all the key concepts related to full adders in digital electronics. Full adders play an important role in many digital electronic circuits because a full adder can be used realize several other critical digital circuits. Print Page Previous Next Advertisements ”;

Digital Electronics – Multiplexers ”; Previous Next A digital logic circuit that accepts several data inputs and allows only one of them at a time to flow through the output is called a multiplexer or MUX. This article is meant for explaining multiplexer in digital electronics, its block diagram, function, and different types. So, let us start with the basic introduction of multiplexer What is a Multiplexer? As already mentioned, a multiplexer, also referred to as MUX, is a combination logic circuit that is designed to accept multiple input signals and transfer only one of them through the output line. In simple words, a multiplexer is a digital logic device that selects one-out-of-N (N = 2n) input data sources and transmits the selected data to a single output line. The multiplexer is also called data selector as it selects one from several. The block diagram of a typical 2n:1 multiplexer is shown in Figure 1. In the case of multiplexer, the selection of desired data input to flow through the output line is controlled with the help of SELECT lines. In the block diagram of mux in Figure 1, I0, I1,… In-1, i.e., (2n) are the input lines, and “n” be the select lines. These select lines will determine which input is to be routed to the output. Hence, the multiplexer works as a multi-position switch whose operation is controlled by digital signals. These digital control signals are applied to the select lines to determine which data input will be switched to the output line. Function of Multiplexer Multiplexer is a digital logic device which is used to perform multiplexing of data. Where, multiplexing simply means sharing of data. Technically, when a particular data is selected from multiple input data sources and transmitted the selected data to a single output channel, it is called multiplexing. There are two types of multiplexing namely, frequency multiplexing and time multiplexing. When multiple devices are connected to a single transmission line in a system. At any point of time, only one device is using the line to transmit data, then this is called time multiplexing. On the other hand, when multiple devices share a common line to transmit data but at different frequencies, it is called frequency multiplexing. Types of Multiplexers Based on input data lines and select lines, the multiplexer can be of several types. But, in this article, we will discuss only the following three types of multiplexers − 2×1 Multiplexer 4×1 Multiplexer Let us discuss each of these three multiplexers individually. 2×1 Multiplexer The block diagram of a 2×1 multiplexer is shown in Figure 2. The 2×1 multiplexer is basic two input multiplexer which has two data input lines designated as I0 and I1, one data select line denoted by S and one output line denoted by Y. The 2×1 mux is used to connect two 1-bit data sources to a common designation. In the 2×1 multiplexer, the logic level of the digital signal applied to the select line S determines which data input will pass through the output line. The operation of the 2×1 multiplexer can be understood from the following truth table. Select Line (S) Output (Y) 0 I0 1 I1 4×1 Multiplexer 4×1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y. The block diagram of 4×1 Multiplexer is shown in the following figure. One of these 4 inputs will be connected to the output based on the combination of inputs present at these two selection lines. Truth table of 4×1 Multiplexer is shown below. Selection Lines Output S1 S0 Y 0 0 I0 0 1 I1 1 0 I2 1 1 I3 From Truth table, we can directly write the Boolean function for output, Y as $$\mathrm{Y:=:{S_{1}}”{S_{0}}”I_{0}:+:{S_{1}}”S_{0}I_{1}:+:S_{1}{S_{0}}”I_{2}:+:S_{1}S_{0}I_{3}}$$ We can implement this Boolean function using Inverters, AND gates & OR gate. The circuit diagram of 4×1 multiplexer is shown in the following figure. We can easily understand the operation of the above circuit. Similarly, you can implement 8×1 Multiplexer and 16×1 multiplexer by following the same procedure. Implementation of Higher-order Multiplexers Now, let us implement the following two higher-order Multiplexers using lower-order Multiplexers. 8×1 Multiplexer 16×1 Multiplexer 8×1 Multiplexer In this section, let us implement 8×1 Multiplexer using 4×1 Multiplexers and 2×1 Multiplexer. We know that 4×1 Multiplexer has 4 data inputs, 2 selection lines and one output. Whereas, 8×1 Multiplexer has 8 data inputs, 3 selection lines and one output. So, we require two 4×1 Multiplexers in first stage in order to get the 8 data inputs. Since, each 4×1 Multiplexer produces one output, we require a 2×1 Multiplexer in second stage by considering the outputs of first stage as inputs and to produce the final output. Let the 8×1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 & s0 and one output Y. The Truth table of 8×1 Multiplexer is shown below. Selection Inputs Output S2 S1 S0 Y 0 0 0 I0 0 0 1 I1 0 1 0 I2 0 1 1 I3 1 0 0 I4 1 0 1 I5 1

Quine-McCluskey Tabular Method ”; Previous Next In this chapter, we will discuss the minimization of Boolean expressions using a tabular method also known as Quine-McCluskey method. The Quine-McCluskey method is more beneficial in minimization of Boolean functions of more than six variables. This minimization technique overcomes the issues associated with K-Map for more than six variables. Another major advantage of Quine-McCluskey method is that it is equally suitable both hand computation and machine computation, as it is programmable. Theory of Quine-McCluskey Method The Quine-McCluskey method is a systematic technique of minimizing complex Boolean expressions. It becomes a suitable method to perform minimization of Boolean expressions of large number of variables. It is also known as tabular method. This minimization technique is based on the repeated use of the combining theorem (i.e., $\mathrm{XA \: + \: X\bar{A} \: = \: X}$, where X is a set of literals) on all adjacent pairs of terms. This process gives a set of all prime implicants, from which we can select a minimal sum. Quine-McCluskey Method Procedure The step-by-step procedure for minimizing a Boolean function by using the Quine McCluskey method is explained below − Step 1 − List all the minterms of the given Boolean expression. Step 2 − Group the minterms. In this step, we arrange all the minterms in groups according to the number of 1s in their binary form. For example, arrange all the minterms with no 1s together, all the minterms with only one 1s together, and so on. The number of 1s in a minterm is called the index of the minterm. Write these grouped minterms in the column 1 of the table. Step 3 − Combine minterms. In this step, compare each minterm of the lowest index group with every minterm in the succeeding group. Whenever possible, combine two minterms in adjacent groups that differ by only 1-bit and replace the differing bit by a dash (-). This represents a don’t care condition. Also, place a check mark (✓) in front of the every minterm that has been combined with at least one minterm. Repeat this process until all possible minterm combinations are made. Write all the combined minterms in the column 2 of the table. Step 4 − Compare and combine the minterms generated in the above step in the same manner. In this step, we combine two minterms which differ by only 1-bit and whose dashes are in the same position. We cannot combine two minterms having dashes in different positions. Write the newly generated terms in the column 3 and put a check mark (✓) next to each term that has been combined in the column 2. Continue this process with terms in column 3, 4, and so on until no further combination is possible. At the end, the terms that are not combined are called the prime implicants. Step 5 − List all the prime implicants and create a prime implicant chart. If there is any don’t care, it should not appear in the prime implicant chart. Step 6 − Select the essential prime implicants which are the prime implicants that cover a minterm which is not covered by any other prime implicant. Step 7 − Combine the essential prime implicants to obtain the final minimized expression. Important Terms Related Quine-McCluskey Method In the Quine-McCluskey method of Boolean expression minimization, several terms are used to convey information. Some key terms related to the Quine-McCluskey method are defined below − Minterm − A minterm is a combination of Boolean variables that has 1 for true value and 0 for false value. Maxterm − A maxterm is a combination of Boolean variables in which true values are designated by 0s and false values are designated by 1s. Index − The number of 1s in a minterm is called its index. Prime Implicant − A minterm that cannot be combined with any other minterm is called a prime implicant. Essential Prime Implicant − A prime implicant that covers at least one minterm which is not covered by any other prime implicant is called an essential prime implicant. Prime Implicant Chart − The graphical representation showing the relationship between the prime implicants and the minterms of the Boolean expression is called the prime implicant chart. Don’t Care Condition − A don’t care condition is a bit or variable that can be ignored during minimization of the function. In Quine-McCluskey method, it is represented by a dash (-). These are some important terms essential to work with the Quine-McCluskey method. Let us now understand the application of Quine-McCluskey method to minimize a Boolean function through an example. Example Based on Quine-McCluskey Method Using the Quine-McCluskey technique minimize the following Boolean function. $$\mathrm{f(A, B,C,D) \: = \: \sum \: m(0,1,5,7,10,14)}$$ Solution The minimization of given Boolean function using the Quine-McCluskey method is explained below. Step 1 − Grouping the given minterms in terms of number of 1s in ascending order and writing their binary form in column 1. Column 1 Index Min Term Binary Form A B C D I0 0 0 0 0 0 I1 1 0 0 0 1 I2 5 0 1 0 1 10 1 0 1 0 I3 7 0 1 1 1 14 1 1 1 0 Step 2 − Comparing and combining minterms of the column 1. Column 1 Column 2

Difference between NAND Gate and NOR Gate ”; Previous Next In digital electronics, logic gates are the basic building blocks of all digital circuits that act as the switching devices in the digital circuits. Therefore, a logic gate is a digital circuit used to perform several logical operations in a digital device or system. A logic gate can accept one or multiple inputs but produces only a single output. Where, the output of a logic gate is determined by the combination of input signals. The operation of the logic gates is based on the Boolean algebra. These days, logic gates are being used in every digital electronic device such as smartphones, laptops, computers, memories, etc. There are many types logic gates available such as AND gate, OR gate, NOT gate, NAND gate, NOR gate, XOR gate, XNOR gate, etc. Here, we will highlight all the differences between NAND gate and NOR gate. Both the NAND gate and the NOR gate are universal logic gates, which means we can implement any logical expression by using the NAND and NOR gates only. Before getting into the differences, let”s start with some basics. What is a NAND Gate? A NAND gate basically a combination of NOT gate and AND gate, i.e. NOT + AND = NAND. Therefore, the NAND gate is a negated version of AND gate. For a NAND gate, the output of the gate is high (1), when all of its inputs are low (0) or at least one input is low. If it has all the inputs low (0), then the gate”s output will be high (1). Hence, from the explanation, it is clear that the NAND gate is an exact inverse of the AND gate. The logical or Boolean expression of a two input NAND gate is given by, $$\mathrm{Y \: = \: \overline{A \cdot B} \: = \: (A \cdot B)^\prime}$$ Where, Y is the output of the NAND gate and A and B are the binary inputs. The NAND gate follows the commutative law, i.e. $$\mathrm{(A \: \cdot \: B)^\prime \: = \: (B \: \cdot \: A)^\prime}$$ Hence, from the Boolean expression of the NAND gate, we can see that the output of the NAND gate is obtained by multiplying all the inputs and then by taking the compliment of the multiplied result. The following is the truth table of a two input NAND gate − Inputs AND Output A B A·B Y = (A·B)” 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 NAND gates are used in realizing other logic gates, making flip-flops, registers, burglar alarm circuit, freezer warning buzzer, etc. What is a NOR Gate? The NOR gate is a combination of NOT and OR gates, i.e. OR + NOT = NOR. A NOR gate consists of an OR gate followed by a NOT gate. For the NOR gate, the output of the gate is high (1), when all its inputs are low (0). In all other cases, it produces a low output. Thus, the NOR gate is nothing but a negated version of the OR gate. The Boolean expression of a two input NOR gate is given by, $$\mathrm{Y \: = \: \overline{A \: + \: B} \: = \: (A \: + \: B)^\prime}$$ Where, Y is the gate”s output and A & B are the inputs. Hence, from the Boolean expression of the NOR gate, it is clear that the gate”s output can be obtained by the logical addition of all the inputs and then taking the complement of the result of addition. The following is the truth table of a two input NOR gate − Inputs OR Output A B A+B Y = (A+B)” 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 0 The NOR gate is used in the realization of several combinational and sequential digital circuits like multiplexers, multipliers, counters, etc. Difference between NAND Gate and NOR Gate NAND and NOR gates are types of universal logic gates, however, there are several differences between these that are listed in the following table − Difference NAND Gate NOR Gate Definition A NAND gate is a universal logic gate which performs the negated logical multiplication. A NOR gate is a universal logic gate which performs the negated logical addition. Implementation NAND gate can be implemented by using an AND gate followed by a NOT gate. NOR gate can be implemented by using an OR gate followed by a NOT gate. Representation The operation of NAND gate can be represented by the complimented AND operation, i.e. (·)”. The operation of a NOR gate can be represented by the complimented OR operation, i.e. (+)”. Boolean Expression The Boolean expression of a two input NAND gate is given by, $\mathrm{Y \: = \: \overline{A \cdot B} \: = \: (A \: \cdot \: B)^\prime}$ The Boolean expression of a two input NOR gate is given by, $\mathrm{Y \: = \: \overline{A \: + \: B} \: = \: (A \: + \: B)^\prime}$ Low Output The NAND gate produces a low (0) output,

Digital Electronics – Families ”; Previous Next A logic family is defined as a set of electronic circuit designs that have similar characteristics in terms of technical parameters such as logic levels, voltage levels, switching speed, power consumption, noise immunity, etc. The logic families play an important role in the field of digital electronics and allows to implement various logic functions and operations. Depending on the fabrication technology, the logic families can be classified into the following two types − Unipolar Logic Family Bipolar Logic Family A logic family that utilizes unipolar electronic devices like MOSFETs as their main element is known as a unipolar logic family. Some examples of unipolar logic families include PMOS, NMOS, and CMOS. On the other hand, a bipolar logic family is one that utilizes bipolar electronic devices such as transistors and diodes. The bipolar logic families can be further classified into the following types − Resistor-Transistor Logic (RTL) Diode Transistor Logic (DTL) Transistor-Transistor Logic (TTL) Let us now discuss about each of these logic families in detail. Resistor-Transistor Logic (RTL) As the name implies, this logic family utilizes resistors and transistors as their key elements. In the RTL family, the transistors operate in the cut-off or saturation regions depending on the input voltage applied to them. The RTL family was one of the earliest logic families used in the field of digital electronic design. In short, in the RTL family, the logic circuits are designed using resistors and transistors only. For example, the circuit of a two-input resistor-transistor logic NOR gate is shown in the following figure. Here, A and B are the inputs and Y is the output of the gate. The operation of this RTL NOR gate for different input combinations is highlighted in the following table − Input A Input B Transistor T1 Transistor T2 Output Y 0 0 Off Off 1 0 1 Off On 0 1 0 On Off 0 1 1 On On 0 Similarly, we can also implement other types of logic gates as well. Advantages of RTL Family The following are some key advantages of resistor-transistor logic family − Electronic circuits designed using RTL logic family are simple in design, as they consist of a minimum number of resistors and transistors. Circuits manufactured in RTL family are less expensive. These circuits consume less amount of power than circuits implemented in other logic families. Disadvantages of RTL Family The following are some major drawbacks of resistor-transistor logic families − RTL circuits have low noise margin. This limitation makes them susceptible to noise and interference. These circuits have poor fan-out. RTL circuits are slower in operation due to high propagation delay. RTL family is not suitable for designing complex circuits due to some practical limitations in terms of design scalability and performance. Applications of RTL Family Resistor-Transistor Logic (RTL) family finds some limited applications in the field of digital electronics. Some common applications of RTL family are listed below − RTL family is cost-effective and easy to understand and design. For this reason, it is widely used for educational purposes in labs and classrooms to demonstrate digital electronic concepts to students. RTL family is also used to design circuits for low-frequency control applications. Due to simplicity and ease of implementation, RTL family can be used for prototyping and experimental purposes. Diode Transistor Logic (DTL) In diode-transistor logic (DTL) family, the diodes and transistors are the key elements combinedly used to implement digital logic functions. The following example circuit demonstrates the electronic circuit design in DTL family. It is a two-input NAND gate. Where, A and B are inputs of the NAND gate and Y is the output of the gate. The operation of this two-input NAND gate is explained in the following truth table − Input A Input B Diode D1 Diode D2 Transistor T Output Y 0 0 Forward biased Forward biased Off 1 0 1 Forward biased Reverse biased Off 1 1 0 Reverse biased Forward biased Off 1 1 1 Reverse biased Reverse biased On 0 We can also implement other types of logic circuits using the diode-transistor logic family. Advantages of DTL Family The following are some key advantages of diode-transistor logic family − DTL circuits are easy and simple to design and implement, as they consist of only diodes, transistors, and resistors. DTL circuits are cost-effective as they use basic electronic components like diodes and transistors which are generally cheap. DTL circuits have good noise immunity. Hence, these circuits are relatively less susceptible to noise and interference than some other types of logic families. DTL circuits have high fan-out. The power dissipation in DTL circuits is comparatively low. Limitations of DTL Family Apart from the advantages given above, the DTL circuits also have some disadvantages which are listed below − DTL family circuits require higher amount of power as compared to other logic families. DTL circuits consist of a greater number of elements than other types of logic families. DTL circuits have a moderate speed of operation. This is due to high propagation delay. DTL circuits are not suitable to design

Programmable Logic Array (PLA) ”; Previous Next In this chapter, we will talk about Programmable Logic Array (PLA), its block diagram, and applications. The programmable logic array (PLA) is a type of programmable logic device (PLD). Historically, PLA is the first PLD device. It contains an array/matrix of AND and OR gates whose configuration is done as per the needs of applications. In a PLA, a set of fusible links is used to establish or remove the contact of a literal in the AND operation or contact of a product term in the OR operation. Therefore, a PLA is a type of PLD that allows both AND matrix and OR matrix to program. In digital electronics, PLAs are used to design and implement a variety of complex combinational circuits. However, some PLAs also have a memory element, hence they can be used to implement sequential circuits as well. Block Diagram of PLA A programmable logic array (PLA) is a type of fixed architecture programmable logic device (PLD) which consists of programmable AND and OR gates. A PLA contains a programmable AND array which is followed by a programmable OR array. The block diagram of the PLA is shown in the following figure − It consists of the following main components − Input Buffer The input buffer is used in PLA to avoid the loading effect on the source that drives the inputs. AND Array/Matrix The AND array/matrix is used in PLA to generate the product terms. OR Array/Matrix In a PLA, the OR array/matrix is used to generate the desired output. This is done by Oring the product terms to produce the sum terms. Invert/Non-Invert Matrix It is a buffer used in PLAs to set the output to active-high or active-low. Output Buffer This buffer is used at the output side. It is mainly provided to increase the driving capability of the programmable logic array (PLA). Combinational Logic Design using PLA In the field of digital electronics, the PLAs are extensively used for designing combinational logic circuits. The greatest advantage of designing combinational circuits using PLAs is that PLA consist of programmable AND and OR arrays which allows to implement custom desired logic functions. The step-by-step procedure to design a combinational logic circuit using PLAs is explained below − Step 1 − Develop a PLA program table that shows the inputs, product terms, and outputs. Step 2 − Design the AND matrix that can generate the desired product terms. Step 3 − Design the OR matrix that can generate the desired output. Step 4 − Design the invert/non-invert matrix to set the active-low or active-high output. Step 5 − Finally, program the PLA by utilizing the PLA program table. Let us understand this process of combinational circuit design using PLA with the help of an example. Example Design a full-adder circuit using programmable logic array (PLA). Solution A full-adder consists of three-inputs and two outputs. Since it has 3 inputs, thus there are total 8 product terms which are given in the following truth table of the full adder − Inputs Outputs A B Cin S Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 From this truth table, the output sum (S) and the output carry (Cout) are given by, $$\mathrm{S \: = \: \sum \: m(1,2,4,7)}$$ $$\mathrm{C_{out} \: = \: \sum \: m(3,5,6,7)}$$ Thus, their Boolean expressions will be, $$\mathrm{S \: = \: \overline{A} \: B \: \overline{C_{in}} \: + \: \overline{A} \: \overline{B} \: C_{in} \: + \: A \: \overline{B} \: \overline{C_{in}} \: + \: A \: B \: C_{in}}$$ $$\mathrm{C_{out} \: = \: A \: B \: + \: B \: C_{in} \: + \: A \: C_{in}}$$ From these two Boolean expressions, we can see that there are seven product terms and two sum terms. The PLA program table for this full-adder circuit is shown below − Sr.No Product Terms Inputs Outputs A B Cin S Cout 1 $\mathrm{\overline{A} \: B \: \overline{C_{in}}}$ 0 1 0 1 – 2 $\mathrm{\overline{A} \: \overline{B} \: C_{in}}$ 0 0 1 1 – 3 $\mathrm{A \: \overline{B} \: \overline{C_{in}}}$ 1 0 0 1 – 4 $\mathrm{A \: B \: C_{in}}$ 1 1 1 1 – 5 $\mathrm{A \: B }$ 1 1 – – 1 6 $\mathrm{B \: C_{in}}$ – 1 1 – 1 7 $\mathrm{A \: C_{in}}$ 1 – 1 – 1 T T In this PLA program table, “1” stands for the connection and “-” stands for the absence of the product term in the output. “T” stands for true and it represents the active-high output. The PLA circuit diagram of

Digital Electronics – Finite State Machines ”; Previous Next Finite State Machines are the fundamental building blocks of various digital and computing systems. They provide a systematic approach to model the behavior of sequential circuits. They also help to control various processes in digital systems. Read this chapter to learn the components, types, advantages, and applications of finite state machines. What is a Finite State Machine? A Finite State Machine (FSM) is a mathematical model that is used to explain and understand the behavior of a digital system. More specifically, it is a structured and systematic model that helps to understand the behavior of a sequential circuit that exists in a finite number of states at a given point of time. In more simple words, a synchronous sequential circuit is also called as Finite State Machine FSM, if it has a finite number of states. The transition of these finite states takes place based on the internal or external inputs that results in the predictable and systematic changes in the behavior of the system. Components of a Finite State Machine A typical finite state machine consists of the following main components − Finite States The finite states are nothing but the distinct modes or conditions in the given system. Each of these finite states represents a specific behavior. In digital system representation, these finite states are generally represented through symbols or labels. State Transitions In terms of finite state machines, the state transition can be defined as the change from one state to another. This change in state or state transition takes placed based on some specific inputs or conditions. These state transitions are generally triggered by events which are associated with some rules or conditions and determine the next state of the system. State Diagram The state transition and the behavior of a finite state machine can be represented in a graphical form that is known as state diagram of the finite state machine. Inputs The inputs to the finite state machines are the external signals that trigger the state transitions in the system. These inputs are to be entered into the finite state machine by using sensors, user input devices like mic, keyboard, etc. Outputs The results produced by the system as per the inputs and current states are known as outputs. These outputs of the system can be used to trigger events, control actuators, or to provide feedback to the external environment. Types of Finite State Machine There are two types of finite state machines namely, Mealy State Machine Moore State Machine Let us now discuss these two types of finite state machines in detail. Mealy State Machine A Finite State Machine is said to be a Mealy state machine, if its outputs depend on both present inputs & present states. The block diagram of the Mealy state machine is shown in the following figure − As shown in the figure, there are two main parts presents in the Mealy state machine. Those are combinational logic circuit and memory element. The memory element is useful to provide some part of previous outputs and present states as inputs to the combinational logic circuit. Based on the present inputs and present states, the Mealy state machine produces outputs. Therefore, the outputs will be valid only at positive or negative transition of the clock signal. State Diagram of Mealy State Machine The state diagram of Mealy state machine is shown in the following figure. In the above figure, there are three states, namely A, B and C. These states are labelled inside the circles and each circle corresponds to one state. State transitions between these states are represented with directed lines. Here, 0 / 0, 1 / 0 and 1 / 1 denote the input / output. In the above figure, there are two state transitions from each state based on the value of input. In general, the number of states required in Mealy state machine is less than or equal to the number of states required in Moore state machine. There is an equivalent Moore state machine for each Mealy state machine. Moore State Machine A Finite State Machine is said to be a Moore state machine, if its outputs depend only on the present states. The block diagram of the Moore state machine is shown in the following figure − As shown in above figure, there are two parts presents in a Moore state machine. Those are combinational logic and memory. In this case, the present inputs and present states determine the next states. So, based on next states, Moore state machine produces the outputs. Therefore, the outputs will be valid only after transition of the state. State Diagram of Moore State Machine The state diagram of Moore state machine is shown in the following figure − In the above figure, there are four states, namely A, B, C, and D. These states and the respective outputs are labelled inside the circles. Here, only the input value is labeled on each transition. In the above figure, there are two transitions from each state based on the value of input. In general, the number of states required in Moore state machine is more than or equal to the number of states required in Mealy state machine. There is an equivalent Mealy state machine for each Moore state machine. So, based on the requirement we can use one of them. Advantages of Finite State Machine The Finite State Machines have several advantages in the field of digital electronics. All these advantages make them a crucial tool for modeling and implementing various digital systems. Some key advantages of Finite State Machines are listed below − Finite

Digital Electronics – Counters ”; Previous Next Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied. Counters are of two types. Asynchronous or Ripple Counters Synchronous Counters Asynchronous or Ripple Counters The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-flop are being used. But we can use the JK flip-flop also with J and K connected permanently to logic 1. External clock is applied to the clock input of flip-flop A and QA output is applied to the clock input of the next flip-flop i.e. FF-B. Logical Diagram Operation Sr.No Condition Operation 1 Initially let both the FFs be in the reset state QBQA = 00 initially 2 After 1st negative clock edge As soon as the first negative clock edge is applied, FF-A will toggle and QA will be equal to 1. QA is connected to clock input of FF-B. Since QA has changed from 0 to 1, it is treated as the positive clock edge by FF-B. There is no change in QB because FF-B is a negative edge triggered FF. QBQA = 01 after the first clock pulse. 3 After 2nd negative clock edge On the arrival of second negative clock edge, FF-A toggles again and QA = 0. The change in QA acts as a negative clock edge for FF-B. So it will also toggle, and QB will be 1. QBQA = 10 after the second clock pulse. 4 After 3rd negative clock edge On the arrival of 3rd negative clock edge, FF-A toggles again and QA become 1 from 0. Since this is a positive going change, FF-B does not respond to it and remains inactive. So QB does not change and continues to be equal to 1. QBQA = 11 after the third clock pulse. 5 After 4th negative clock edge On the arrival of 4th negative clock edge, FF-A toggles again and QA becomes 1 from 0. This negative change in QA acts as clock pulse for FF-B. Hence it toggles to change QB from 1 to 0. QBQA = 00 after the fourth clock pulse. Truth Table Synchronous Counters If the “clock” pulses are applied to all the flip-flops in a counter simultaneously, then such a counter is called as synchronous counter. 2-bit Synchronous Up Counter The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle flip-flop. The JB and KB inputs are connected to QA. Logical Diagram Operation Sr.No Condition Operation 1 Initially let both the FFs be in the reset state QBQA = 00 initially. 2 After 1st negative clock edge As soon as the first negative clock edge is applied, FF-A will toggle and QA will change from 0 to 1. But at the instant of application of negative clock edge, QA , JB = KB = 0. Hence FF-B will not change its state. So QB will remain 0. QBQA = 01 after the first clock pulse. 3 After 2nd negative clock edge On the arrival of second negative clock edge, FF-A toggles again and QA changes from 1 to 0. But at this instant QA was 1. So JB = KB= 1 and FF-B will toggle. Hence QB changes from 0 to 1. QBQA = 10 after the second clock pulse. 4 After 3rd negative clock edge On application of the third falling clock edge, FF-A will toggle from 0 to 1 but there is no change of state for FF-B. QBQA = 11 after the third clock pulse. 5 After 4th negative clock edge On application of the next clock pulse, QA will change from 1 to 0 as QB will also change from 1 to 0. QBQA = 00 after the fourth clock pulse. Classification of Counters Depending on the way in which the counting progresses, the synchronous or asynchronous counters are classified as follows − Up Counters Down Counters Up/Down Counters UP/DOWN Counter Up counter and down counter is combined together to obtain an UP/DOWN counter. A mode control (M) input is also provided to select either up or down mode. A combinational circuit is required to be designed and used between each pair of flip-flop in order to achieve the up/down operation. Type of Up/Down Counters There are two types of up/down counters − UP/DOWN Ripple Counters UP/DOWN Synchronous Counter UP/DOWN Ripple Counters In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So either T flip-flops or JK flip-flops are to be used. The LSB flip-flop receives clock directly. But the clock to every other FF is obtained from (Q = Q bar) output of the previous FF. UP counting mode (M=0) − The Q output of the preceding FF is connected to the clock of the next stage if up counting is to be achieved. For this mode, the mode select input M is at logic 0 (M=0). DOWN counting mode (M=1) − If M = 1, then the Q bar

Digital Electronics – Shift Registers ”; Previous Next Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To increase the storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a group of flip-flop is known as a Register. The n-bit register will consist of n number of flip-flop and it is capable of storing an n-bit word. The binary data in a register can be moved within the register from one flip-flop to another. The registers that allow such data transfers are called as shift registers. There are four mode of operations of a shift register. Serial In – Serial Out (SISO) Shift Register Serial In – Parallel Out (SIPO) Shift Register Parallel In – Serial Out (PISO) Shift Register Parallel In – Parallel Out (PIPO) Shift Register Serial In – Serial Out (SISO) Shift Register Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If an entry of a four bit binary number 1 1 1 1 is made into the register, this number should be applied to Din bit with the LSB bit applied first. The D input of FF-3 i.e. D3 is connected to serial data input Din. Output of FF-3 i.e. Q3 is connected to the input of the next flip-flop i.e. D2 and so on. Block Diagram Operation Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the number to be entered to Din. So Din = D3 = 1. Apply the clock. On the first falling edge of clock, the FF-3 is set, and stored word in the register is Q3 Q2 Q1 Q0 = 1000. Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock hits, FF-2 will set and the stored word change to Q3 Q2 Q1 Q0 = 1100. Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third negative clock edge hits, FF-1 will be set and output will be modified to Q3 Q2 Q1 Q0 = 1110. Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored word in the register is Q3 Q2 Q1 Q0 = 1111. Truth Table Waveforms Serial In – Parallel Out (SIPO) Shift Register In such types of operations, the data is entered serially and taken out in parallel fashion. Data is loaded bit by bit. The outputs are disabled as long as the data is loading. As soon as the data loading gets completed, all the flip-flops contain their required data, the outputs are enabled so that all the loaded data is made available over all the output lines at the same time. 4 clock cycles are required to load a four bit word. Hence the speed of operation of SIPO mode is same as that of SISO mode. Block Diagram Parallel In – Serial Out (PISO) Shift Register Data bits are entered in parallel fashion. The circuit shown below is a four bit parallel input serial output register. Output of previous Flip Flop is connected to the input of the next one via a combinational circuit. The binary input word B0, B1, B2, B3 is applied though the same combinational circuit. There are two modes in which this circuit can work namely – shift mode or load mode. Load Mode When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active they will pass B1, B2, B3 bits to the corresponding flip-flops. On the low going edge of clock, the binary input B0, B1, B2, B3 will get loaded into the corresponding flip-flops. Thus parallel loading takes place. Shift Mode When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive. Hence the parallel loading of the data becomes impossible. But the AND gate 1,3 and 5 become active. Therefore the shifting of data from left to right bit by bit on application of clock pulses. Thus the parallel in serial out operation takes place. Block Diagram Parallel In – Parallel Out (PIPO) Shift Register In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1, D2, D3 respectively of the four flip-flops. As soon as a negative clock edge is applied, the input binary bits will be loaded into the flip-flops simultaneously. The loaded bits will appear simultaneously to the output side. Only clock pulse is essential to load all the bits. Block Diagram Bidirectional Shift Register If a binary number is shifted left by one position then it is equivalent to multiplying the original number by 2. Similarly if a binary number is shifted right by one position then it is equivalent to dividing the original number by 2. Hence if we want to use the shift register to multiply and divide the given binary number, then we should be able to move the data in either left or right direction. Such a register is called bi-directional register. A four bit bi-directional shift register is shown in fig. There are two serial inputs namely the serial right shift data input DR, and the serial left shift data input DL along with a mode select input (M). Block Diagram Operation Sr.No Condition Operation 1 With M = 1 − Shift right operation